diff --git a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v
index bb17bc9..955a177 100644
--- a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v
+++ b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v
@@ -6,7 +6,7 @@
 `define FPGA_PROG_CLOCK_PERIOD 12.5
 `define FPGA_CLOCK_PERIOD 12.5
 
-module ccff_test_caravel;
+module ccff_test_post_pnr_caravel_autocheck_top_tb;
   reg clock;
   reg RSTB;
   reg power1, power2;
diff --git a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v
index 021aae2..97dd641 100644
--- a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v
+++ b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v
@@ -5,7 +5,7 @@
 `define SOC_CLOCK_PERIOD 12.5
 `define FPGA_CLOCK_PERIOD 12.5
 
-module scff_test_caravel;
+module scff_test_post_pnr_caravel_autocheck_top_tb;
   reg clock;
   reg RSTB;
   reg power1, power2;