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[QLSOFA] Bugfix to fix floating cin net

This commit is contained in:
Ganesh Gore 2020-12-22 00:22:29 -07:00
parent 562641ed4d
commit e1a25d61dc
58 changed files with 4225 additions and 1563 deletions
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1
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SDC/disable_configure_ports.sdc
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@ -4,7 +4,6 @@
# Description: Disable configuration outputs of all the programmable cells for PnR
# Author: Xifan TANG
# Organization: University of Utah
# Date: Sun Dec 13 03:08:29 2020
#############################################
set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram

20
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/fabric_netlists.v
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@ -12,16 +12,16 @@
`include "./SRC/fpga_defines.v"
//
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v"
`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v"
//
`include "./SRC/sub_module/inv_buf_passgate.v"
`include "./SRC/sub_module/arch_encoder.v"

54
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v
View File

@ -76,7 +76,8 @@ wire [0:0] fabric_cout;
wire [0:0] direct_interc_10_out;
wire [0:0] direct_interc_11_out;
wire [0:0] direct_interc_2_out;
wire [0:0] direct_interc_12_out;
wire [0:0] direct_interc_13_out;
wire [0:0] direct_interc_3_out;
wire [0:0] direct_interc_4_out;
wire [0:0] direct_interc_5_out;
@ -87,9 +88,8 @@ wire [0:0] direct_interc_9_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout;
wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin;
wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout;
wire [0:1] mux_fabric_out_0_undriven_sram_inv;
wire [0:1] mux_fabric_out_1_undriven_sram_inv;
wire [0:1] mux_ff_0_D_0_undriven_sram_inv;
@ -112,28 +112,28 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 (
.pReset(pReset[0]),
.prog_clk(prog_clk[0]),
.frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}),
.frac_logic_cin(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin[0]),
.frac_logic_in({direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0]}),
.frac_logic_cin(direct_interc_7_out[0]),
.ccff_head(ccff_head[0]),
.frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]),
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout[0]),
.frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
.ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_2_out[0]),
.ff_DI(direct_interc_6_out[0]),
.ff_reset(direct_interc_7_out[0]),
.ff_DI(direct_interc_8_out[0]),
.ff_reset(direct_interc_9_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.ff_clk(direct_interc_8_out[0]));
.ff_clk(direct_interc_10_out[0]));
logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 (
.Test_en(Test_en[0]),
.ff_D(mux_tree_size2_3_out[0]),
.ff_DI(direct_interc_9_out[0]),
.ff_reset(direct_interc_10_out[0]),
.ff_DI(direct_interc_11_out[0]),
.ff_reset(direct_interc_12_out[0]),
.ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]),
.ff_clk(direct_interc_11_out[0]));
.ff_clk(direct_interc_13_out[0]));
mux_tree_size2 mux_fabric_out_0 (
.in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}),
@ -196,45 +196,53 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail;
.out(fabric_sc_out[0]));
direct_interc direct_interc_2_ (
.in(fabric_in[0]),
.out(direct_interc_2_out[0]));
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]),
.out(fabric_cout[0]));
direct_interc direct_interc_3_ (
.in(fabric_in[1]),
.in(fabric_in[0]),
.out(direct_interc_3_out[0]));
direct_interc direct_interc_4_ (
.in(fabric_in[2]),
.in(fabric_in[1]),
.out(direct_interc_4_out[0]));
direct_interc direct_interc_5_ (
.in(fabric_in[3]),
.in(fabric_in[2]),
.out(direct_interc_5_out[0]));
direct_interc direct_interc_6_ (
.in(fabric_sc_in[0]),
.in(fabric_in[3]),
.out(direct_interc_6_out[0]));
direct_interc direct_interc_7_ (
.in(fabric_reset[0]),
.in(fabric_cin[0]),
.out(direct_interc_7_out[0]));
direct_interc direct_interc_8_ (
.in(fabric_clk[0]),
.in(fabric_sc_in[0]),
.out(direct_interc_8_out[0]));
direct_interc direct_interc_9_ (
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.in(fabric_reset[0]),
.out(direct_interc_9_out[0]));
direct_interc direct_interc_10_ (
.in(fabric_reset[0]),
.in(fabric_clk[0]),
.out(direct_interc_10_out[0]));
direct_interc direct_interc_11_ (
.in(fabric_clk[0]),
.in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]),
.out(direct_interc_11_out[0]));
direct_interc direct_interc_12_ (
.in(fabric_reset[0]),
.out(direct_interc_12_out[0]));
direct_interc direct_interc_13_ (
.in(fabric_clk[0]),
.out(direct_interc_13_out[0]));
endmodule
//

1
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml
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@ -2,7 +2,6 @@
- Fabric bitstream
- Author: Xifan TANG
- Organization: University of Utah
- Date: Sun Dec 13 03:08:25 2020
-->
<fabric_bitstream>

1
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml
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@ -2,7 +2,6 @@
- Architecture independent bitstream
- Author: Xifan TANG
- Organization: University of Utah
- Date: Sun Dec 13 03:08:24 2020
-->
<bitstream_block name="fpga_top" hierarchy_level="0">

428
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/openfpgashell.log
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@ -1,4 +1,4 @@
/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga
/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga
Reading script file top_run.openfpga...
___ _____ ____ ____ _
@ -72,51 +72,17 @@ Warning 9: Model 'carry_follower' input port 'a' has no timing specification (no
Warning 10: Model 'carry_follower' output port 'cout' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.01 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB)
# Building complex block graph
Warning 11: clb[0].cin[0] unconnected pin in architecture.
Warning 12: clb[0].cout[0] unconnected pin in architecture.
Warning 13: fle[0].cin[0] unconnected pin in architecture.
Warning 14: fle[0].cout[0] unconnected pin in architecture.
Warning 15: fle[1].cin[0] unconnected pin in architecture.
Warning 16: fle[1].cout[0] unconnected pin in architecture.
Warning 17: fle[2].cin[0] unconnected pin in architecture.
Warning 18: fle[2].cout[0] unconnected pin in architecture.
Warning 19: fle[3].cin[0] unconnected pin in architecture.
Warning 20: fle[3].cout[0] unconnected pin in architecture.
Warning 21: fle[4].cin[0] unconnected pin in architecture.
Warning 22: fle[4].cout[0] unconnected pin in architecture.
Warning 23: fle[5].cin[0] unconnected pin in architecture.
Warning 24: fle[5].cout[0] unconnected pin in architecture.
Warning 25: fle[6].cin[0] unconnected pin in architecture.
Warning 26: fle[6].cout[0] unconnected pin in architecture.
Warning 27: fle[7].cin[0] unconnected pin in architecture.
Warning 28: fle[7].cout[0] unconnected pin in architecture.
Warning 29: fabric[0].cin[0] unconnected pin in architecture.
Warning 30: fabric[0].cout[0] unconnected pin in architecture.
Warning 31: fabric[0].cin[0] unconnected pin in architecture.
Warning 32: fabric[0].cout[0] unconnected pin in architecture.
Warning 33: fabric[0].cin[0] unconnected pin in architecture.
Warning 34: fabric[0].cout[0] unconnected pin in architecture.
Warning 35: fabric[0].cin[0] unconnected pin in architecture.
Warning 36: fabric[0].cout[0] unconnected pin in architecture.
Warning 37: fabric[0].cin[0] unconnected pin in architecture.
Warning 38: fabric[0].cout[0] unconnected pin in architecture.
Warning 39: fabric[0].cin[0] unconnected pin in architecture.
Warning 40: fabric[0].cout[0] unconnected pin in architecture.
Warning 41: fabric[0].cin[0] unconnected pin in architecture.
Warning 42: fabric[0].cout[0] unconnected pin in architecture.
Warning 43: fabric[0].cin[0] unconnected pin in architecture.
Warning 44: fabric[0].cout[0] unconnected pin in architecture.
Warning 45: [LINE 652] false logically-equivalent pin clb[0].I0[1].
Warning 46: [LINE 658] false logically-equivalent pin clb[0].I1[1].
Warning 47: [LINE 664] false logically-equivalent pin clb[0].I2[1].
Warning 48: [LINE 670] false logically-equivalent pin clb[0].I3[1].
Warning 49: [LINE 676] false logically-equivalent pin clb[0].I4[1].
Warning 50: [LINE 682] false logically-equivalent pin clb[0].I5[1].
Warning 51: [LINE 688] false logically-equivalent pin clb[0].I6[1].
Warning 52: [LINE 694] false logically-equivalent pin clb[0].I7[1].
Warning 11: [LINE 654] false logically-equivalent pin clb[0].I0[1].
Warning 12: [LINE 660] false logically-equivalent pin clb[0].I1[1].
Warning 13: [LINE 666] false logically-equivalent pin clb[0].I2[1].
Warning 14: [LINE 672] false logically-equivalent pin clb[0].I3[1].
Warning 15: [LINE 678] false logically-equivalent pin clb[0].I4[1].
Warning 16: [LINE 684] false logically-equivalent pin clb[0].I5[1].
Warning 17: [LINE 690] false logically-equivalent pin clb[0].I6[1].
Warning 18: [LINE 696] false logically-equivalent pin clb[0].I7[1].
# Building complex block graph took 0.01 seconds (max_rss 9.6 MiB, delta_rss +0.8 MiB)
# Load circuit
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.3 MiB)
# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB)
# Clean circuit
Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred 0 additional primitive pins as constant generators due to constant inputs
@ -224,10 +190,10 @@ RoutingArch.switch_block_type: WILTON
RoutingArch.Fs: 3
# Packing
Warning 53: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 54: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 55: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 56: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 19: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 20: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 21: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 22: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Begin packing 'top.blif'.
After removing unused inputs...
@ -237,10 +203,10 @@ Finish prepacking.
Using inter-cluster delay: 1.33777e-09
Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1
Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32
Warning 57: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 58: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 59: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 60: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 23: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 24: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 25: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 26: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Not enough resources expand FPGA size to (14 x 14)
Complex block 0: 'c' (clb) .
Complex block 1: 'out:c' (io) .
@ -269,10 +235,10 @@ Logic Element (fle) detailed count:
io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667
clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1
Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed.
Warning 61: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 62: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 63: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 64: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 28: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 29: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 30: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 14 x 14 (12x12)
Device Utilization: 0.02 (target 1.00)
Block Utilization: 0.02 Type: io
@ -287,9 +253,9 @@ Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'.
Detected 0 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.01 seconds).
Warning 65: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
Warning 31: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity).
# Load Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB)
Warning 66: Netlist contains 0 global net to non-global architecture pin connections
Warning 32: Netlist contains 0 global net to non-global architecture pin connections
Netlist num_nets: 3
Netlist num_blocks: 4
@ -301,10 +267,10 @@ Netlist output pins: 1
# Create Device
## Build Device Grid
Warning 67: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 68: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 69: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 70: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 33: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 34: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply.
Warning 35: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
Warning 36: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply.
FPGA sized to 14 x 14: 196 grid tiles (12x12)
Resource usage...
@ -332,98 +298,98 @@ Device Utilization: 0.02 (target 1.00)
Physical Tile clb:
Block Utilization: 0.01 Logical Block: clb
## Build Device Grid took 0.00 seconds (max_rss 10.8 MiB, delta_rss +0.0 MiB)
## Build Device Grid took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB)
## Build tileable routing resource graph
X-direction routing channel width is 60
Y-direction routing channel width is 60
Warning 71: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 72: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 73: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 74: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 75: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 76: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 77: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 78: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 79: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 80: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 81: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 82: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 83: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 84: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 85: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 86: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 87: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 88: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 89: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 90: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 91: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 92: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 93: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 94: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 95: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 96: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 97: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 98: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 99: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 100: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 101: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 102: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 103: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 104: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 105: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 106: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 107: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
Warning 37: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 38: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 39: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 40: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 41: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 42: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 43: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 44: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 45: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 46: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 47: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 48: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 49: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 50: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 51: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 52: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 53: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 54: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 55: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 56: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 57: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 58: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 59: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 60: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 61: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 62: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 63: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 64: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 65: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 66: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 67: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 68: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 69: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 70: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 71: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 72: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 73: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
## Build tileable routing resource graph took 0.21 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
## Build tileable routing resource graph took 0.22 seconds (max_rss 20.1 MiB, delta_rss +7.3 MiB)
RR Graph Nodes: 23404
RR Graph Edges: 121880
# Create Device took 0.21 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB)
# Create Device took 0.22 seconds (max_rss 20.1 MiB, delta_rss +7.3 MiB)
# Placement
## Computing placement delta delay look-up
### Build routing resource graph
Warning 108: in check_rr_node: RR node: 184 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 109: in check_rr_node: RR node: 185 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 110: in check_rr_node: RR node: 186 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 111: in check_rr_node: RR node: 1472 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 112: in check_rr_node: RR node: 1473 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 113: in check_rr_node: RR node: 1474 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 114: in check_rr_node: RR node: 2760 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 115: in check_rr_node: RR node: 2761 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 116: in check_rr_node: RR node: 2762 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 117: in check_rr_node: RR node: 4048 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 118: in check_rr_node: RR node: 4049 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 119: in check_rr_node: RR node: 4050 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 120: in check_rr_node: RR node: 5336 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 121: in check_rr_node: RR node: 5337 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 122: in check_rr_node: RR node: 5338 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 123: in check_rr_node: RR node: 6624 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 124: in check_rr_node: RR node: 6625 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 125: in check_rr_node: RR node: 6626 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 126: in check_rr_node: RR node: 7912 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 127: in check_rr_node: RR node: 7913 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 128: in check_rr_node: RR node: 7914 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 129: in check_rr_node: RR node: 9200 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 130: in check_rr_node: RR node: 9201 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 131: in check_rr_node: RR node: 9202 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 132: in check_rr_node: RR node: 10488 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 133: in check_rr_node: RR node: 10489 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 134: in check_rr_node: RR node: 10490 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 135: in check_rr_node: RR node: 11776 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 136: in check_rr_node: RR node: 11777 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 137: in check_rr_node: RR node: 11778 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 138: in check_rr_node: RR node: 13064 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 139: in check_rr_node: RR node: 13065 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 140: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 141: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 142: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 143: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
### Build routing resource graph took 0.15 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
Warning 74: in check_rr_node: RR node: 184 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 75: in check_rr_node: RR node: 185 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 76: in check_rr_node: RR node: 186 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 77: in check_rr_node: RR node: 1472 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 78: in check_rr_node: RR node: 1473 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 79: in check_rr_node: RR node: 1474 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 80: in check_rr_node: RR node: 2760 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 81: in check_rr_node: RR node: 2761 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 82: in check_rr_node: RR node: 2762 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 83: in check_rr_node: RR node: 4048 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 84: in check_rr_node: RR node: 4049 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 85: in check_rr_node: RR node: 4050 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 86: in check_rr_node: RR node: 5336 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 87: in check_rr_node: RR node: 5337 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 88: in check_rr_node: RR node: 5338 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 89: in check_rr_node: RR node: 6624 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 90: in check_rr_node: RR node: 6625 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 91: in check_rr_node: RR node: 6626 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 92: in check_rr_node: RR node: 7912 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 93: in check_rr_node: RR node: 7913 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 94: in check_rr_node: RR node: 7914 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 95: in check_rr_node: RR node: 9200 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 96: in check_rr_node: RR node: 9201 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 97: in check_rr_node: RR node: 9202 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 98: in check_rr_node: RR node: 10488 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 99: in check_rr_node: RR node: 10489 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 100: in check_rr_node: RR node: 10490 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 101: in check_rr_node: RR node: 11776 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 102: in check_rr_node: RR node: 11777 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 103: in check_rr_node: RR node: 11778 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 104: in check_rr_node: RR node: 13064 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 105: in check_rr_node: RR node: 13065 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 106: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 107: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 108: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 109: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
### Build routing resource graph took 0.10 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
RR Graph Nodes: 23120
RR Graph Edges: 105560
### Computing delta delays
### Computing delta delays took 0.04 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB)
## Computing placement delta delay look-up took 0.20 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
## Computing placement delta delay look-up took 0.14 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB)
There are 3 point to point connections in this circuit.
@ -526,49 +492,49 @@ Placement total # of swap attempts: 232
Swaps aborted : 0 ( 0.0 %)
Aborted Move Reasons:
# Placement took 0.20 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
# Placement took 0.15 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB)
# Routing
## Build tileable routing resource graph
X-direction routing channel width is 60
Y-direction routing channel width is 60
Warning 144: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 145: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 146: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 147: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 148: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 149: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 150: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 151: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 152: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 153: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 154: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 155: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 156: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 157: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 158: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 159: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 160: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 161: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 162: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 163: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 164: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 165: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 166: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 167: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 168: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 169: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 170: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 171: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 172: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 173: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 174: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 175: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 176: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 177: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 178: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 179: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 180: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
Warning 110: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 111: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 112: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 113: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 114: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 115: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 116: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 117: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 118: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 119: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 120: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 121: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 122: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 123: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 124: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 125: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 126: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 127: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 128: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 129: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 130: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 131: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 132: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 133: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 134: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 135: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 136: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 137: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 138: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 139: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 140: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 141: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 142: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 143: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges.
Warning 144: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges.
Warning 145: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges.
Warning 146: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin.
This is possible on a fringe node based on low Fc_out, N, and certain lengths.
## Build tileable routing resource graph took 0.19 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB)
RR Graph Nodes: 23404
@ -583,7 +549,7 @@ Restoring best routing
Critical path: 0.69331 ns
Successfully routed after 1 routing iterations.
Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 124 total_heap_pops: 52
# Routing took 0.19 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB)
# Routing took 0.19 seconds (max_rss 22.4 MiB, delta_rss +1.1 MiB)
Checking to ensure routing is legal...
Completed routing consistency check successfully.
@ -701,9 +667,9 @@ Setup slack histogram:
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
[ -6.9e-10: -6.9e-10) 0 ( 0.0%) |
Timing analysis took 0.000335007 seconds (0.000304377 STA, 3.063e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
Timing analysis took 0.000322969 seconds (0.000292792 STA, 3.0177e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined).
VPR suceeded
The entire flow of VPR took 0.68 seconds (max_rss 22.4 MiB)
The entire flow of VPR took 0.63 seconds (max_rss 22.5 MiB)
Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
@ -711,10 +677,10 @@ Confirm selected options when call command 'read_openfpga_arch':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml
Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'...
Read OpenFPGA architecture
Warning 181: Automatically set circuit model 'frac_lut4' to be default in its type.
Warning 182: Automatically set circuit model 'sky130_fd_sc_hd__sdfrtp_1' to be default in its type.
Warning 183: Automatically set circuit model 'sky130_fd_sc_hd__mux2_1_wrapper' to be default in its type.
Warning 184: Automatically set circuit model 'sky130_fd_sc_hd__dfrtp_1' to be default in its type.
Warning 147: Automatically set circuit model 'frac_lut4' to be default in its type.
Warning 148: Automatically set circuit model 'sky130_fd_sc_hd__sdfrtp_1' to be default in its type.
Warning 149: Automatically set circuit model 'sky130_fd_sc_hd__mux2_1_wrapper' to be default in its type.
Warning 150: Automatically set circuit model 'sky130_fd_sc_hd__dfrtp_1' to be default in its type.
Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree_tapbuf' port 'sram')
Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'frac_lut4' port 'sram')
@ -725,11 +691,11 @@ Check circuit library took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB)
Found 0 errors when checking configurable memory circuit models!
Found 0 errors when checking tile annotation!
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Confirm selected options when call command 'read_openfpga_simulation_setting':
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
--file, -f: /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'...
Read OpenFPGA simulation settings
Read OpenFPGA simulation settings took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.1 MiB)
@ -1122,21 +1088,21 @@ Average net density: 0.42
Median net density: 0.00
Average net density after weighting: 0.42
Will apply 2 operating clock cycles to simulations
Link OpenFPGA architecture to VPR architecture took 0.10 seconds (max_rss 23.5 MiB, delta_rss +0.7 MiB)
Link OpenFPGA architecture to VPR architecture took 0.11 seconds (max_rss 23.6 MiB, delta_rss +0.7 MiB)
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml
Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml
Confirm selected options when call command 'build_fabric':
--frame_view: off
--compress_routing: on
--duplicate_grid_pin: on
--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml
--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml
--write_fabric_key: off
--generate_random_fabric_key: off
--verbose: off
Identify unique General Switch Blocks (GSBs)
Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%)
Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.5 MiB, delta_rss +0.0 MiB)
Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB)
Read Fabric Key
Read Fabric Key took 0.00 seconds (max_rss 23.6 MiB, delta_rss +0.1 MiB)
@ -1157,7 +1123,7 @@ Build fabric module graph
# Build wire modules
# Build wire modules took 0.00 seconds (max_rss 23.9 MiB, delta_rss +0.0 MiB)
# Build memory modules
# Build memory modules took 0.00 seconds (max_rss 24.1 MiB, delta_rss +0.3 MiB)
# Build memory modules took 0.00 seconds (max_rss 24.2 MiB, delta_rss +0.3 MiB)
# Build grid modules
Building logical tiles...Done
Building physical tiles...Done
@ -1166,40 +1132,40 @@ Building physical tiles...Done
# Build unique routing modules... took 0.02 seconds (max_rss 27.8 MiB, delta_rss +3.1 MiB)
# Build FPGA fabric module
## Add grid instances to top module
## Add grid instances to top module took 0.00 seconds (max_rss 29.0 MiB, delta_rss +1.3 MiB)
## Add grid instances to top module took 0.00 seconds (max_rss 29.1 MiB, delta_rss +1.3 MiB)
## Add switch block instances to top module
## Add switch block instances to top module took 0.00 seconds (max_rss 29.8 MiB, delta_rss +0.8 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 30.3 MiB, delta_rss +0.5 MiB)
## Add connection block instances to top module
## Add connection block instances to top module took 0.00 seconds (max_rss 30.8 MiB, delta_rss +0.5 MiB)
## Add connection block instances to top module took 0.00 seconds (max_rss 30.9 MiB, delta_rss +0.5 MiB)
## Add module nets between grids and GSBs
## Add module nets between grids and GSBs took 0.18 seconds (max_rss 52.2 MiB, delta_rss +21.4 MiB)
## Add module nets between grids and GSBs took 0.17 seconds (max_rss 52.3 MiB, delta_rss +21.4 MiB)
## Add module nets for inter-tile connections
## Add module nets for inter-tile connections took 0.00 seconds (max_rss 52.8 MiB, delta_rss +0.5 MiB)
## Add module nets for configuration buses
## Add module nets for configuration buses took 0.02 seconds (max_rss 54.6 MiB, delta_rss +1.5 MiB)
# Build FPGA fabric module took 0.22 seconds (max_rss 54.6 MiB, delta_rss +26.8 MiB)
Build fabric module graph took 0.24 seconds (max_rss 54.6 MiB, delta_rss +30.9 MiB)
## Add module nets for configuration buses took 0.02 seconds (max_rss 56.1 MiB, delta_rss +2.8 MiB)
# Build FPGA fabric module took 0.21 seconds (max_rss 56.1 MiB, delta_rss +28.3 MiB)
Build fabric module graph took 0.24 seconds (max_rss 56.1 MiB, delta_rss +32.4 MiB)
Create I/O location mapping for top module
Create I/O location mapping for top module took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB)
Create I/O location mapping for top module took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB)
Create global port info for top module
Create global port info for top module took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB)
Create global port info for top module took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB)
Command line to execute: repack
Confirm selected options when call command 'repack':
--verbose: off
Build routing resource graph for the physical implementation of logical tile
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB)
Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile
Repack clustered block 'c'...Done
Repack clustered block 'out:c'...Done
Repack clustered block 'a'...Done
Repack clustered block 'b'...Done
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB)
Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs
Build truth tables for physical LUTs took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB)
Build truth tables for physical LUTs took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB)
Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml
@ -1215,10 +1181,10 @@ Generating bitstream for X-direction Connection blocks ...Done
Generating bitstream for Y-direction Connection blocks ...Done
Build fabric-independent bitstream for implementation 'top'
took 0.18 seconds (max_rss 60.0 MiB, delta_rss +5.5 MiB)
Warning 185: Directory path is empty and nothing will be created.
took 0.16 seconds (max_rss 61.3 MiB, delta_rss +5.3 MiB)
Warning 151: Directory path is empty and nothing will be created.
Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml'
Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.54 seconds (max_rss 60.0 MiB, delta_rss +0.0 MiB)
Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.53 seconds (max_rss 61.3 MiB, delta_rss +0.0 MiB)
Command line to execute: build_fabric_bitstream
@ -1229,7 +1195,7 @@ Build fabric dependent bitstream
Build fabric dependent bitstream
took 0.09 seconds (max_rss 64.9 MiB, delta_rss +4.9 MiB)
took 0.04 seconds (max_rss 66.2 MiB, delta_rss +4.9 MiB)
Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit
@ -1237,9 +1203,9 @@ Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.bit
--format: plain_text
--verbose: off
Warning 186: Directory path is empty and nothing will be created.
Warning 152: Directory path is empty and nothing will be created.
Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit'
Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.02 seconds (max_rss 64.9 MiB, delta_rss +0.0 MiB)
Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.02 seconds (max_rss 66.2 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml
@ -1247,9 +1213,9 @@ Confirm selected options when call command 'write_fabric_bitstream':
--file, -f: fabric_bitstream.xml
--format: xml
--verbose: off
Warning 187: Directory path is empty and nothing will be created.
Warning 153: Directory path is empty and nothing will be created.
Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml'
Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.13 seconds (max_rss 65.0 MiB, delta_rss +0.1 MiB)
Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.10 seconds (max_rss 66.2 MiB, delta_rss +0.0 MiB)
Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose
@ -1312,7 +1278,7 @@ Building physical tiles...Done
Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done
Written 71 Verilog modules in total
Write Verilog netlists for FPGA fabric
took 0.52 seconds (max_rss 67.9 MiB, delta_rss +2.8 MiB)
took 0.42 seconds (max_rss 69.1 MiB, delta_rss +2.9 MiB)
Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
@ -1329,22 +1295,22 @@ Confirm selected options when call command 'write_verilog_testbench':
--include_signal_init: off
--support_icarus_simulator: off
--verbose: off
Warning 188: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
Warning 154: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled
Write Verilog testbenches for FPGA fabric
Warning 189: Directory './SRC' already exists. Will overwrite contents
Warning 155: Directory './SRC' already exists. Will overwrite contents
# Write pre-configured FPGA top-level Verilog netlist for design 'top'
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 2.73 seconds (max_rss 67.9 MiB, delta_rss +0.1 MiB)
# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 2.65 seconds (max_rss 69.2 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top'
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB)
# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 69.2 MiB, delta_rss +0.0 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top'
Will use 78766 configuration clock cycles to top testbench
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.20 seconds (max_rss 68.0 MiB, delta_rss +0.1 MiB)
# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.14 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB)
Succeed to create directory './SimulationDeck'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini'
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 68.0 MiB, delta_rss +0.0 MiB)
# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB)
Write Verilog testbenches for FPGA fabric
took 2.96 seconds (max_rss 68.0 MiB, delta_rss +0.1 MiB)
took 2.82 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB)
Command line to execute: write_pnr_sdc --file ./SDC
@ -1366,19 +1332,19 @@ Confirm selected options when call command 'write_pnr_sdc':
--verbose: off
Succeed to create directory './SDC'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc'
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 68.0 MiB, delta_rss +0.0 MiB)
Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB)
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc'
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.00 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB)
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc'
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.03 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.04 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB)
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc'
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.02 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Switch Block timing for P&R flow
Write SDC for constrain Switch Block timing for P&R flow took 0.03 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Switch Block timing for P&R flow took 0.04 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Connection Block timing for P&R flow
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB)
Write SDC for constraining grid timing for P&R flow
Write SDC for constraining grid timing for P&R flow took 0.04 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB)
Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
@ -1386,9 +1352,9 @@ Confirm selected options when call command 'write_sdc_disable_timing_configure_p
--file, -f: ./SDC/disable_configure_ports.sdc
--flatten_names: off
--verbose: off
Warning 190: Directory './SDC' already exists. Will overwrite contents
Warning 156: Directory './SDC' already exists. Will overwrite contents
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc'
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.10 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.06 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB)
Command line to execute: write_analysis_sdc --file ./SDC_analysis
@ -1399,7 +1365,7 @@ Confirm selected options when call command 'write_analysis_sdc':
--time_unit: off
Succeed to create directory './SDC_analysis'
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc'
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 1.06 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB)
Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.85 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB)
Command line to execute: exit
@ -1407,6 +1373,6 @@ Confirm selected options when call command 'exit':
Finish execution with 0 errors
The entire OpenFPGA flow took 6.57 seconds
The entire OpenFPGA flow took 5.93 seconds
Thank you for using OpenFPGA!

1
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/proj_const.tcl
View File

@ -2,6 +2,7 @@ set DIE_HEIGHT 3200
set DIE_WIDTH 3200
set DESIGN_NAME fpga_core
set TASK_NAME FPGA1212_QLSOFA_HD_task
set PROJ_NAME FPGA1212_QLSOFA_HD
set VERILOG_PROJ_DIR FPGA1212_QLSOFA_HD_Verilog
set FPGA_ROW 12
set FPGA_COL 12

36
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__0__scandef.def
View File

@ -0,0 +1,36 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__1__scandef.def
View File

@ -0,0 +1,64 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__2__scandef.def
View File

@ -0,0 +1,64 @@
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
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mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
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mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

4
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_0__1__scandef.def
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mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_1__1__scandef.def
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mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
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mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
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mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_
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mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_
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mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_
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mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

64
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_2__1__scandef.def
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mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_
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mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_

1232
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/grid_clb_scandef.def
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File diff suppressed because it is too large Load Diff

76
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__0__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
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mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_42/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_58/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_58/sky130_fd_sc_hd__dfxtp_1_1_

132
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__1__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
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mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
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mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
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mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_

132
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__2__scandef.def
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@ -0,0 +1,132 @@
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
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mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_
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mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_

135
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__0__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
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mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
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164
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__1__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
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164
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__2__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
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mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_
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mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_
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mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_
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mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_

135
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__0__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
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mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_
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mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
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mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
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mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_
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mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
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mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_
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mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_

164
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__1__scandef.def
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mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
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mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
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mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
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mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_

164
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__2__scandef.def
View File

@ -0,0 +1,164 @@
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_
mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_
mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_
mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_

10
FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml
View File

@ -447,10 +447,12 @@
</pb_type>
<interconnect>
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
<direct name="direct2" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct3" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct4" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct5" input="ff[1].Q" output="fabric.reg_out"/>
<direct name="direct2" input="fabric.cin" output="frac_logic.cin"/>
<direct name="direct3" input="fabric.sc_in" output="ff[0].DI"/>
<direct name="direct4" input="ff[0].Q" output="ff[1].DI"/>
<direct name="direct5" input="ff[1].Q" output="fabric.sc_out"/>
<direct name="direct6" input="ff[1].Q" output="fabric.reg_out"/>
<direct name="direct7" input="frac_logic.cout" output="fabric.cout"/>
<complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
<complete name="complete2" input="fabric.reset" output="ff[1:0].reset"/>
<mux name="mux1" input="frac_logic.out[0:0] fabric.reg_in" output="ff[0:0].D">

2
FPGA1212_QLSOFA_HD_PNR/config.sh
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@ -24,7 +24,7 @@ export DIE_DIMENSION=3200
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Derived Or Fixed Variables
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip
export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH}
export TASK_DIR_NAME=${PROJ_NAME}_task
export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog
export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt

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2
FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv
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@ -15,4 +15,4 @@
|fpga_core_uut/cby_0__12_ | 23.46 | 6406.144000 | 5120 | 12 | 815
|fpga_core_uut/cby_11__12_ | 82.05 | 6406.144000 | 5120 | 132 | 444
|fpga_core_uut/cby_12__12_ | 82.64 | 6406.144000 | 5120 | 12 | 486
|fpga_core_uut/grid_clb_12__12_ | 68.26 | 14814.208000 | 11840 | 144 | 1370
|fpga_core_uut/grid_clb_12__12_ | 68.3 | 14814.208000 | 11840 | 144 | 1083

1 | Module | Util| Area| Sites| Insts| Std_Cells
15 |fpga_core_uut/cby_0__12_ | 23.46 | 6406.144000 | 5120 | 12 | 815
16 |fpga_core_uut/cby_11__12_ | 82.05 | 6406.144000 | 5120 | 132 | 444
17 |fpga_core_uut/cby_12__12_ | 82.64 | 6406.144000 | 5120 | 12 | 486
18 |fpga_core_uut/grid_clb_12__12_ | 68.26 | 14814.208000 | 11840 | 144 | 1370 |fpga_core_uut/grid_clb_12__12_ | 68.3 | 14814.208000 | 11840 | 144 | 1083

14
FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv
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@ -1,31 +1,31 @@
Ref Name Total Area Utilization_% Instance Count
----------------------------------------------------------------------------------------------------
sky130_fd_sc_hd__dfrtp_1 1971015.360000 19.18 78765
sky130_fd_sc_hd__mux2_1 1591488.864000 15.49 141330
sky130_fd_sc_hd__mux2_1 1602839.750400 15.60 142338
sky130_fd_sc_hd__buf_8 452744.217600 4.41 30154
sky130_fd_sc_hd__buf_6 150252.854400 1.46 13343
sky130_fd_sc_hd__buf_6 148631.299200 1.45 13199
sky130_fd_sc_hd__buf_1 88960.320000 0.87 23700
sky130_fd_sc_hd__inv_8 76584.700800 0.75 6801
sky130_fd_sc_hd__inv_8 78206.256000 0.76 6945
sky130_fd_sc_hd__sdfrtp_1 72069.120000 0.70 2304
sky130_fd_sc_hd__dlygate4sd3_1 56293.990400 0.55 5624
sky130_fd_sc_hd__mux2_2 44311.248000 0.43 3935
sky130_fd_sc_hd__inv_1 42156.681600 0.41 11231
sky130_fd_sc_hd__buf_4 39112.512000 0.38 5210
sky130_fd_sc_hd__buf_4 36950.438400 0.36 4922
sky130_fd_sc_hd__bufbuf_16 36239.756800 0.35 1114
sky130_fd_sc_hd__mux2_2 32960.361600 0.32 2927
sky130_fd_sc_hd__conb_1 25592.044800 0.25 6818
sky130_fd_sc_hd__inv_2 13696.886400 0.13 3649
sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152
sky130_fd_sc_hd__inv_6 6235.980800 0.06 712
sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354
sky130_fd_sc_hd__clkbuf_1 2747.635200 0.03 732
sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020
sky130_fd_sc_hd__dlygate4sd2_1 2417.318400 0.02 276
sky130_fd_sc_hd__clkbuf_8 2147.059200 0.02 156
sky130_fd_sc_hd__buf_2 1436.377600 0.01 287
sky130_fd_sc_hd__dlygate4sd1_1 1366.310400 0.01 156
sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132
sky130_fd_sc_hd__buf_16 633.107200 0.01 23
sky130_fd_sc_hd__inv_4 450.432000 0.00 72
sky130_fd_sc_hd__buf_12 220.211200 0.00 11
sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12
sky130_fd_sc_hd__or2b_4 135.129600 0.00 12
FPGA_BBOX_AREA 6714279.5264
CORE_BBOX_AREA 10276128.1216

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18
FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt
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@ -6,7 +6,7 @@ Report : clock timing
-setup
Design : fpga_top
Version: P-2019.03-SP4
Date : Mon Dec 14 01:56:02 2020
Date : Mon Dec 21 23:13:06 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.143 11.143 rp-+ nominal
fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.140 11.140 rp-+ nominal
---------------------------------------------------------------------------------------------------
Mode: full_chip
@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
--- Latency ---
Clock Pin Trans Source Offset Network Total Corner
---------------------------------------------------------------------------------------------------
fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.710 0.000 -- 6.927 6.927 rp-+ nominal
fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.701 0.000 -- 6.921 6.921 rp-+ nominal
---------------------------------------------------------------------------------------------------
****************************************
Report : clock timing
@ -34,7 +34,7 @@ Report : clock timing
-setup
Design : fpga_top
Version: P-2019.03-SP4
Date : Mon Dec 14 01:56:02 2020
Date : Mon Dec 21 23:13:07 2020
****************************************
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
Clock Pin Latency Skew Corner
---------------------------------------------------------------------------------------------------
fpga_core_uut/sb_10__8_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 9.828 rp-+ nominal
fpga_core_uut/cbx_10__8_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 5.994 3.835 rp-+ nominal
fpga_core_uut/sb_1__5_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 10.371 rp-+ nominal
fpga_core_uut/cbx_1__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 6.542 3.829 rp-+ nominal
---------------------------------------------------------------------------------------------------
@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
Clock Pin Latency Skew Corner
---------------------------------------------------------------------------------------------------
fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.115 rp-+ nominal
fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.386 0.729 rp-+ nominal
fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.109 rp-+ nominal
fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.381 0.729 rp-+ nominal
---------------------------------------------------------------------------------------------------
Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050)
@ -63,7 +63,7 @@ Report : global timing
-format { narrow }
Design : fpga_top
Version: P-2019.03-SP4
Date : Mon Dec 14 01:56:04 2020
Date : Mon Dec 21 23:13:09 2020
****************************************
No setup violations found.

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