diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SDC/disable_configure_ports.sdc b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SDC/disable_configure_ports.sdc index c136e0d..8c6bc89 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SDC/disable_configure_ports.sdc +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SDC/disable_configure_ports.sdc @@ -4,7 +4,6 @@ # Description: Disable configuration outputs of all the programmable cells for PnR # Author: Xifan TANG # Organization: University of Utah -# Date: Sun Dec 13 03:08:29 2020 ############################################# set_disable_timing fpga_core_uut/grid_clb_*__*_/logical_tile_clb_mode_clb__*/logical_tile_clb_mode_default__fle_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_*/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut*_*/frac_lut*_*_/sram diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/fabric_netlists.v b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/fabric_netlists.v index a34efa8..0261176 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/fabric_netlists.v +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/fabric_netlists.v @@ -12,16 +12,16 @@ `include "./SRC/fpga_defines.v" // -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" -`include "/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_2.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/buf/sky130_fd_sc_hd__buf_4.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/inv/sky130_fd_sc_hd__inv_2.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/or2/sky130_fd_sc_hd__or2_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/mux2/sky130_fd_sc_hd__mux2_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/sdfrtp/sky130_fd_sc_hd__sdfrtp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/skywater/libraries/sky130_fd_sc_hd/latest/cells/dfrtp/sky130_fd_sc_hd__dfrtp_1.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/digital_io_hd.v" +`include "/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA22_HIER_SKY_PNR/sc_verilog/sky130_fd_sc_hd_wrapper.v" // `include "./SRC/sub_module/inv_buf_passgate.v" `include "./SRC/sub_module/arch_encoder.v" diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v index 4ac614a..aed4e47 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/lb/logical_tile_clb_mode_default__fle_mode_physical__fabric.v @@ -76,7 +76,8 @@ wire [0:0] fabric_cout; wire [0:0] direct_interc_10_out; wire [0:0] direct_interc_11_out; -wire [0:0] direct_interc_2_out; +wire [0:0] direct_interc_12_out; +wire [0:0] direct_interc_13_out; wire [0:0] direct_interc_3_out; wire [0:0] direct_interc_4_out; wire [0:0] direct_interc_5_out; @@ -87,9 +88,8 @@ wire [0:0] direct_interc_9_out; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail; +wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout; wire [0:1] mux_fabric_out_0_undriven_sram_inv; wire [0:1] mux_fabric_out_1_undriven_sram_inv; wire [0:1] mux_ff_0_D_0_undriven_sram_inv; @@ -112,28 +112,28 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail; logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset(pReset[0]), .prog_clk(prog_clk[0]), - .frac_logic_in({direct_interc_2_out[0], direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0]}), - .frac_logic_cin(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin[0]), + .frac_logic_in({direct_interc_3_out[0], direct_interc_4_out[0], direct_interc_5_out[0], direct_interc_6_out[0]}), + .frac_logic_cin(direct_interc_7_out[0]), .ccff_head(ccff_head[0]), .frac_logic_out(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0:1]), - .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cout[0]), + .frac_logic_cout(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]), .ccff_tail(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail[0])); logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en(Test_en[0]), .ff_D(mux_tree_size2_2_out[0]), - .ff_DI(direct_interc_6_out[0]), - .ff_reset(direct_interc_7_out[0]), + .ff_DI(direct_interc_8_out[0]), + .ff_reset(direct_interc_9_out[0]), .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), - .ff_clk(direct_interc_8_out[0])); + .ff_clk(direct_interc_10_out[0])); logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1 ( .Test_en(Test_en[0]), .ff_D(mux_tree_size2_3_out[0]), - .ff_DI(direct_interc_9_out[0]), - .ff_reset(direct_interc_10_out[0]), + .ff_DI(direct_interc_11_out[0]), + .ff_reset(direct_interc_12_out[0]), .ff_Q(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1_ff_Q[0]), - .ff_clk(direct_interc_11_out[0])); + .ff_clk(direct_interc_13_out[0])); mux_tree_size2 mux_fabric_out_0 ( .in({logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0], logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0]}), @@ -196,45 +196,53 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail; .out(fabric_sc_out[0])); direct_interc direct_interc_2_ ( - .in(fabric_in[0]), - .out(direct_interc_2_out[0])); + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_cout[0]), + .out(fabric_cout[0])); direct_interc direct_interc_3_ ( - .in(fabric_in[1]), + .in(fabric_in[0]), .out(direct_interc_3_out[0])); direct_interc direct_interc_4_ ( - .in(fabric_in[2]), + .in(fabric_in[1]), .out(direct_interc_4_out[0])); direct_interc direct_interc_5_ ( - .in(fabric_in[3]), + .in(fabric_in[2]), .out(direct_interc_5_out[0])); direct_interc direct_interc_6_ ( - .in(fabric_sc_in[0]), + .in(fabric_in[3]), .out(direct_interc_6_out[0])); direct_interc direct_interc_7_ ( - .in(fabric_reset[0]), + .in(fabric_cin[0]), .out(direct_interc_7_out[0])); direct_interc direct_interc_8_ ( - .in(fabric_clk[0]), + .in(fabric_sc_in[0]), .out(direct_interc_8_out[0])); direct_interc direct_interc_9_ ( - .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), + .in(fabric_reset[0]), .out(direct_interc_9_out[0])); direct_interc direct_interc_10_ ( - .in(fabric_reset[0]), + .in(fabric_clk[0]), .out(direct_interc_10_out[0])); direct_interc direct_interc_11_ ( - .in(fabric_clk[0]), + .in(logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0]), .out(direct_interc_11_out[0])); + direct_interc direct_interc_12_ ( + .in(fabric_reset[0]), + .out(direct_interc_12_out[0])); + + direct_interc direct_interc_13_ ( + .in(fabric_clk[0]), + .out(direct_interc_13_out[0])); + endmodule // diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml index aebe375..9d0c367 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_bitstream.xml @@ -2,7 +2,6 @@ - Fabric bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Sun Dec 13 03:08:25 2020 --> diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml index aa2c307..7b22ecd 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/TESTBENCH/top/fabric_indepenent_bitstream.xml @@ -2,7 +2,6 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Sun Dec 13 03:08:24 2020 --> diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/openfpgashell.log b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/openfpgashell.log index f679f45..e98715d 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/openfpgashell.log +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/openfpgashell.log @@ -1,4 +1,4 @@ -/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga +/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga/openfpga -f top_run.openfpga Reading script file top_run.openfpga... ___ _____ ____ ____ _ @@ -72,51 +72,17 @@ Warning 9: Model 'carry_follower' input port 'a' has no timing specification (no Warning 10: Model 'carry_follower' output port 'cout' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output) # Loading Architecture Description took 0.01 seconds (max_rss 8.8 MiB, delta_rss +0.4 MiB) # Building complex block graph -Warning 11: clb[0].cin[0] unconnected pin in architecture. -Warning 12: clb[0].cout[0] unconnected pin in architecture. -Warning 13: fle[0].cin[0] unconnected pin in architecture. -Warning 14: fle[0].cout[0] unconnected pin in architecture. -Warning 15: fle[1].cin[0] unconnected pin in architecture. -Warning 16: fle[1].cout[0] unconnected pin in architecture. -Warning 17: fle[2].cin[0] unconnected pin in architecture. -Warning 18: fle[2].cout[0] unconnected pin in architecture. -Warning 19: fle[3].cin[0] unconnected pin in architecture. -Warning 20: fle[3].cout[0] unconnected pin in architecture. -Warning 21: fle[4].cin[0] unconnected pin in architecture. -Warning 22: fle[4].cout[0] unconnected pin in architecture. -Warning 23: fle[5].cin[0] unconnected pin in architecture. -Warning 24: fle[5].cout[0] unconnected pin in architecture. -Warning 25: fle[6].cin[0] unconnected pin in architecture. -Warning 26: fle[6].cout[0] unconnected pin in architecture. -Warning 27: fle[7].cin[0] unconnected pin in architecture. -Warning 28: fle[7].cout[0] unconnected pin in architecture. -Warning 29: fabric[0].cin[0] unconnected pin in architecture. -Warning 30: fabric[0].cout[0] unconnected pin in architecture. -Warning 31: fabric[0].cin[0] unconnected pin in architecture. -Warning 32: fabric[0].cout[0] unconnected pin in architecture. -Warning 33: fabric[0].cin[0] unconnected pin in architecture. -Warning 34: fabric[0].cout[0] unconnected pin in architecture. -Warning 35: fabric[0].cin[0] unconnected pin in architecture. -Warning 36: fabric[0].cout[0] unconnected pin in architecture. -Warning 37: fabric[0].cin[0] unconnected pin in architecture. -Warning 38: fabric[0].cout[0] unconnected pin in architecture. -Warning 39: fabric[0].cin[0] unconnected pin in architecture. -Warning 40: fabric[0].cout[0] unconnected pin in architecture. -Warning 41: fabric[0].cin[0] unconnected pin in architecture. -Warning 42: fabric[0].cout[0] unconnected pin in architecture. -Warning 43: fabric[0].cin[0] unconnected pin in architecture. -Warning 44: fabric[0].cout[0] unconnected pin in architecture. -Warning 45: [LINE 652] false logically-equivalent pin clb[0].I0[1]. -Warning 46: [LINE 658] false logically-equivalent pin clb[0].I1[1]. -Warning 47: [LINE 664] false logically-equivalent pin clb[0].I2[1]. -Warning 48: [LINE 670] false logically-equivalent pin clb[0].I3[1]. -Warning 49: [LINE 676] false logically-equivalent pin clb[0].I4[1]. -Warning 50: [LINE 682] false logically-equivalent pin clb[0].I5[1]. -Warning 51: [LINE 688] false logically-equivalent pin clb[0].I6[1]. -Warning 52: [LINE 694] false logically-equivalent pin clb[0].I7[1]. +Warning 11: [LINE 654] false logically-equivalent pin clb[0].I0[1]. +Warning 12: [LINE 660] false logically-equivalent pin clb[0].I1[1]. +Warning 13: [LINE 666] false logically-equivalent pin clb[0].I2[1]. +Warning 14: [LINE 672] false logically-equivalent pin clb[0].I3[1]. +Warning 15: [LINE 678] false logically-equivalent pin clb[0].I4[1]. +Warning 16: [LINE 684] false logically-equivalent pin clb[0].I5[1]. +Warning 17: [LINE 690] false logically-equivalent pin clb[0].I6[1]. +Warning 18: [LINE 696] false logically-equivalent pin clb[0].I7[1]. # Building complex block graph took 0.01 seconds (max_rss 9.6 MiB, delta_rss +0.8 MiB) # Load circuit -# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.3 MiB) +# Load circuit took 0.00 seconds (max_rss 9.9 MiB, delta_rss +0.4 MiB) # Clean circuit Inferred 0 additional primitive pins as constant generators since they have no combinationally connected inputs Inferred 0 additional primitive pins as constant generators due to constant inputs @@ -224,10 +190,10 @@ RoutingArch.switch_block_type: WILTON RoutingArch.Fs: 3 # Packing -Warning 53: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 54: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 55: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 56: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 19: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 20: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 21: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 22: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Begin packing 'top.blif'. After removing unused inputs... @@ -237,10 +203,10 @@ Finish prepacking. Using inter-cluster delay: 1.33777e-09 Packing with pin utilization targets: io_top:1,1 io_right:1,1 io_bottom:1,1 io_left:1,1 clb:0.8,1 Packing with high fanout thresholds: io_top:128 io_right:128 io_bottom:128 io_left:128 clb:32 -Warning 57: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 58: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 59: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 60: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 23: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 24: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 25: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 26: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. Not enough resources expand FPGA size to (14 x 14) Complex block 0: 'c' (clb) . Complex block 1: 'out:c' (io) . @@ -269,10 +235,10 @@ Logic Element (fle) detailed count: io: # blocks: 3, average # input + clock pins used: 0.333333, average # output pins used: 0.666667 clb: # blocks: 1, average # input + clock pins used: 2, average # output pins used: 1 Absorbed logical nets 0 out of 3 nets, 3 nets not absorbed. -Warning 61: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 62: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 63: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 64: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 27: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 28: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 29: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 30: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 14 x 14 (12x12) Device Utilization: 0.02 (target 1.00) Block Utilization: 0.02 Type: io @@ -287,9 +253,9 @@ Begin loading packed FPGA netlist file. Netlist generated from file 'top.net'. Detected 0 constant generators (to see names run with higher pack verbosity) Finished loading packed FPGA netlist file (took 0.01 seconds). -Warning 65: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). +Warning 31: Treated 0 constant nets as global which will not be routed (to see net names increase packer verbosity). # Load Packing took 0.01 seconds (max_rss 10.7 MiB, delta_rss +0.1 MiB) -Warning 66: Netlist contains 0 global net to non-global architecture pin connections +Warning 32: Netlist contains 0 global net to non-global architecture pin connections Netlist num_nets: 3 Netlist num_blocks: 4 @@ -301,10 +267,10 @@ Netlist output pins: 1 # Create Device ## Build Device Grid -Warning 67: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 68: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. -Warning 69: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. -Warning 70: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 33: Ambiguous block type specification at grid location (0,0). Existing block type 'io_bottom' at (0,0) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 34: Ambiguous block type specification at grid location (0,13). Existing block type 'io_top' at (0,13) has the same priority (100) as new overlapping type 'io_left'. The last specification will apply. +Warning 35: Ambiguous block type specification at grid location (13,0). Existing block type 'io_bottom' at (13,0) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. +Warning 36: Ambiguous block type specification at grid location (13,13). Existing block type 'io_top' at (13,13) has the same priority (100) as new overlapping type 'io_right'. The last specification will apply. FPGA sized to 14 x 14: 196 grid tiles (12x12) Resource usage... @@ -332,98 +298,98 @@ Device Utilization: 0.02 (target 1.00) Physical Tile clb: Block Utilization: 0.01 Logical Block: clb -## Build Device Grid took 0.00 seconds (max_rss 10.8 MiB, delta_rss +0.0 MiB) +## Build Device Grid took 0.00 seconds (max_rss 12.8 MiB, delta_rss +0.0 MiB) ## Build tileable routing resource graph X-direction routing channel width is 60 Y-direction routing channel width is 60 -Warning 71: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 72: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 73: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 74: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 75: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 76: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 77: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 78: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 79: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 80: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 81: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 82: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 83: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 84: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 85: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 86: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 87: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 88: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 89: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 90: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 91: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 92: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 93: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 94: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 95: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 96: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 97: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 98: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 99: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 100: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 101: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 102: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 103: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 104: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 105: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 106: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 107: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. +Warning 37: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 38: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 39: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 40: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 41: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 42: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 43: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 44: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 45: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 46: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 47: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 48: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 49: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 50: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 51: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 52: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 53: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 54: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 55: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 56: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 57: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 58: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 59: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 60: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 61: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 62: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 63: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 64: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 65: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 66: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 67: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 68: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 69: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 70: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 71: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 72: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 73: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. This is possible on a fringe node based on low Fc_out, N, and certain lengths. -## Build tileable routing resource graph took 0.21 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) +## Build tileable routing resource graph took 0.22 seconds (max_rss 20.1 MiB, delta_rss +7.3 MiB) RR Graph Nodes: 23404 RR Graph Edges: 121880 -# Create Device took 0.21 seconds (max_rss 20.1 MiB, delta_rss +9.3 MiB) +# Create Device took 0.22 seconds (max_rss 20.1 MiB, delta_rss +7.3 MiB) # Placement ## Computing placement delta delay look-up ### Build routing resource graph -Warning 108: in check_rr_node: RR node: 184 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 109: in check_rr_node: RR node: 185 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 110: in check_rr_node: RR node: 186 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 111: in check_rr_node: RR node: 1472 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 112: in check_rr_node: RR node: 1473 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 113: in check_rr_node: RR node: 1474 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 114: in check_rr_node: RR node: 2760 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 115: in check_rr_node: RR node: 2761 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 116: in check_rr_node: RR node: 2762 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 117: in check_rr_node: RR node: 4048 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 118: in check_rr_node: RR node: 4049 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 119: in check_rr_node: RR node: 4050 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 120: in check_rr_node: RR node: 5336 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 121: in check_rr_node: RR node: 5337 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 122: in check_rr_node: RR node: 5338 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 123: in check_rr_node: RR node: 6624 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 124: in check_rr_node: RR node: 6625 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 125: in check_rr_node: RR node: 6626 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 126: in check_rr_node: RR node: 7912 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 127: in check_rr_node: RR node: 7913 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 128: in check_rr_node: RR node: 7914 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 129: in check_rr_node: RR node: 9200 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 130: in check_rr_node: RR node: 9201 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 131: in check_rr_node: RR node: 9202 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 132: in check_rr_node: RR node: 10488 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 133: in check_rr_node: RR node: 10489 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 134: in check_rr_node: RR node: 10490 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 135: in check_rr_node: RR node: 11776 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 136: in check_rr_node: RR node: 11777 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 137: in check_rr_node: RR node: 11778 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 138: in check_rr_node: RR node: 13064 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 139: in check_rr_node: RR node: 13065 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 140: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 141: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 142: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 143: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -### Build routing resource graph took 0.15 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) +Warning 74: in check_rr_node: RR node: 184 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 75: in check_rr_node: RR node: 185 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 76: in check_rr_node: RR node: 186 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 77: in check_rr_node: RR node: 1472 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 78: in check_rr_node: RR node: 1473 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 79: in check_rr_node: RR node: 1474 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 80: in check_rr_node: RR node: 2760 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 81: in check_rr_node: RR node: 2761 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 82: in check_rr_node: RR node: 2762 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 83: in check_rr_node: RR node: 4048 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 84: in check_rr_node: RR node: 4049 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 85: in check_rr_node: RR node: 4050 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 86: in check_rr_node: RR node: 5336 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 87: in check_rr_node: RR node: 5337 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 88: in check_rr_node: RR node: 5338 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 89: in check_rr_node: RR node: 6624 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 90: in check_rr_node: RR node: 6625 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 91: in check_rr_node: RR node: 6626 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 92: in check_rr_node: RR node: 7912 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 93: in check_rr_node: RR node: 7913 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 94: in check_rr_node: RR node: 7914 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 95: in check_rr_node: RR node: 9200 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 96: in check_rr_node: RR node: 9201 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 97: in check_rr_node: RR node: 9202 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 98: in check_rr_node: RR node: 10488 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 99: in check_rr_node: RR node: 10489 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 100: in check_rr_node: RR node: 10490 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 101: in check_rr_node: RR node: 11776 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 102: in check_rr_node: RR node: 11777 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 103: in check_rr_node: RR node: 11778 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 104: in check_rr_node: RR node: 13064 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 105: in check_rr_node: RR node: 13065 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 106: in check_rr_node: RR node: 13066 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 107: in check_rr_node: RR node: 14352 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 108: in check_rr_node: RR node: 14353 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 109: in check_rr_node: RR node: 14354 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +### Build routing resource graph took 0.10 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) RR Graph Nodes: 23120 RR Graph Edges: 105560 ### Computing delta delays ### Computing delta delays took 0.04 seconds (max_rss 20.8 MiB, delta_rss +0.0 MiB) -## Computing placement delta delay look-up took 0.20 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) +## Computing placement delta delay look-up took 0.14 seconds (max_rss 20.8 MiB, delta_rss +0.5 MiB) There are 3 point to point connections in this circuit. @@ -526,49 +492,49 @@ Placement total # of swap attempts: 232 Swaps aborted : 0 ( 0.0 %) Aborted Move Reasons: -# Placement took 0.20 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB) +# Placement took 0.15 seconds (max_rss 21.2 MiB, delta_rss +1.1 MiB) # Routing ## Build tileable routing resource graph X-direction routing channel width is 60 Y-direction routing channel width is 60 -Warning 144: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 145: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 146: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 147: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 148: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 149: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 150: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 151: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 152: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 153: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 154: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 155: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 156: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 157: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 158: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 159: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 160: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 161: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 162: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 163: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 164: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 165: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 166: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 167: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 168: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 169: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 170: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 171: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 172: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 173: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 174: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 175: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 176: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 177: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. -Warning 178: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. -Warning 179: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. -Warning 180: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. +Warning 110: in check_rr_node: RR node: 500 type: OPIN location: (1,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 111: in check_rr_node: RR node: 501 type: OPIN location: (1,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 112: in check_rr_node: RR node: 502 type: OPIN location: (1,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 113: in check_rr_node: RR node: 604 type: OPIN location: (2,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 114: in check_rr_node: RR node: 605 type: OPIN location: (2,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 115: in check_rr_node: RR node: 606 type: OPIN location: (2,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 116: in check_rr_node: RR node: 708 type: OPIN location: (3,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 117: in check_rr_node: RR node: 709 type: OPIN location: (3,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 118: in check_rr_node: RR node: 710 type: OPIN location: (3,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 119: in check_rr_node: RR node: 812 type: OPIN location: (4,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 120: in check_rr_node: RR node: 813 type: OPIN location: (4,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 121: in check_rr_node: RR node: 814 type: OPIN location: (4,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 122: in check_rr_node: RR node: 916 type: OPIN location: (5,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 123: in check_rr_node: RR node: 917 type: OPIN location: (5,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 124: in check_rr_node: RR node: 918 type: OPIN location: (5,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 125: in check_rr_node: RR node: 1020 type: OPIN location: (6,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 126: in check_rr_node: RR node: 1021 type: OPIN location: (6,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 127: in check_rr_node: RR node: 1022 type: OPIN location: (6,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 128: in check_rr_node: RR node: 1124 type: OPIN location: (7,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 129: in check_rr_node: RR node: 1125 type: OPIN location: (7,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 130: in check_rr_node: RR node: 1126 type: OPIN location: (7,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 131: in check_rr_node: RR node: 1228 type: OPIN location: (8,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 132: in check_rr_node: RR node: 1229 type: OPIN location: (8,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 133: in check_rr_node: RR node: 1230 type: OPIN location: (8,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 134: in check_rr_node: RR node: 1332 type: OPIN location: (9,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 135: in check_rr_node: RR node: 1333 type: OPIN location: (9,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 136: in check_rr_node: RR node: 1334 type: OPIN location: (9,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 137: in check_rr_node: RR node: 1436 type: OPIN location: (10,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 138: in check_rr_node: RR node: 1437 type: OPIN location: (10,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 139: in check_rr_node: RR node: 1438 type: OPIN location: (10,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 140: in check_rr_node: RR node: 1540 type: OPIN location: (11,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 141: in check_rr_node: RR node: 1541 type: OPIN location: (11,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 142: in check_rr_node: RR node: 1542 type: OPIN location: (11,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 143: in check_rr_node: RR node: 1644 type: OPIN location: (12,1) pin: 52 pin_name: clb.reg_out[0] capacity: 1 has no out-going edges. +Warning 144: in check_rr_node: RR node: 1645 type: OPIN location: (12,1) pin: 53 pin_name: clb.sc_out[0] capacity: 1 has no out-going edges. +Warning 145: in check_rr_node: RR node: 1646 type: OPIN location: (12,1) pin: 54 pin_name: clb.cout[0] capacity: 1 has no out-going edges. +Warning 146: in check_rr_graph: fringe node 15912 CHANX at (1,1) has no fanin. This is possible on a fringe node based on low Fc_out, N, and certain lengths. ## Build tileable routing resource graph took 0.19 seconds (max_rss 21.5 MiB, delta_rss +0.3 MiB) RR Graph Nodes: 23404 @@ -583,7 +549,7 @@ Restoring best routing Critical path: 0.69331 ns Successfully routed after 1 routing iterations. Router Stats: total_nets_routed: 3 total_connections_routed: 3 total_heap_pushes: 124 total_heap_pops: 52 -# Routing took 0.19 seconds (max_rss 22.3 MiB, delta_rss +1.1 MiB) +# Routing took 0.19 seconds (max_rss 22.4 MiB, delta_rss +1.1 MiB) Checking to ensure routing is legal... Completed routing consistency check successfully. @@ -701,9 +667,9 @@ Setup slack histogram: [ -6.9e-10: -6.9e-10) 0 ( 0.0%) | [ -6.9e-10: -6.9e-10) 0 ( 0.0%) | -Timing analysis took 0.000335007 seconds (0.000304377 STA, 3.063e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined). +Timing analysis took 0.000322969 seconds (0.000292792 STA, 3.0177e-05 slack) (43 full updates: 41 setup, 0 hold, 2 combined). VPR suceeded -The entire flow of VPR took 0.68 seconds (max_rss 22.4 MiB) +The entire flow of VPR took 0.63 seconds (max_rss 22.5 MiB) Command line to execute: read_openfpga_arch -f /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml @@ -711,10 +677,10 @@ Confirm selected options when call command 'read_openfpga_arch': --file, -f: /research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml Reading XML architecture '/research/ece/lnis/USERS/DARPA_ERI/GF14nm_chip_2019/ICC2_Methodology_Flow/GANESH/FROG_PnR/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/run001/vpr_arch/top/MIN_ROUTE_CHAN_WIDTH/arch/openfpga_arch.xml'... Read OpenFPGA architecture -Warning 181: Automatically set circuit model 'frac_lut4' to be default in its type. -Warning 182: Automatically set circuit model 'sky130_fd_sc_hd__sdfrtp_1' to be default in its type. -Warning 183: Automatically set circuit model 'sky130_fd_sc_hd__mux2_1_wrapper' to be default in its type. -Warning 184: Automatically set circuit model 'sky130_fd_sc_hd__dfrtp_1' to be default in its type. +Warning 147: Automatically set circuit model 'frac_lut4' to be default in its type. +Warning 148: Automatically set circuit model 'sky130_fd_sc_hd__sdfrtp_1' to be default in its type. +Warning 149: Automatically set circuit model 'sky130_fd_sc_hd__mux2_1_wrapper' to be default in its type. +Warning 150: Automatically set circuit model 'sky130_fd_sc_hd__dfrtp_1' to be default in its type. Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'mux_tree_tapbuf' port 'sram') Use the default configurable memory model 'sky130_fd_sc_hd__dfrtp_1' for circuit model 'frac_lut4' port 'sram') @@ -725,11 +691,11 @@ Check circuit library took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.0 MiB) Found 0 errors when checking configurable memory circuit models! Found 0 errors when checking tile annotation! -Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +Command line to execute: read_openfpga_simulation_setting -f /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml Confirm selected options when call command 'read_openfpga_simulation_setting': ---file, -f: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... +--file, -f: /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +Reading XML simulation setting '/research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml'... Read OpenFPGA simulation settings Read OpenFPGA simulation settings took 0.00 seconds (max_rss 22.8 MiB, delta_rss +0.1 MiB) @@ -1122,21 +1088,21 @@ Average net density: 0.42 Median net density: 0.00 Average net density after weighting: 0.42 Will apply 2 operating clock cycles to simulations -Link OpenFPGA architecture to VPR architecture took 0.10 seconds (max_rss 23.5 MiB, delta_rss +0.7 MiB) +Link OpenFPGA architecture to VPR architecture took 0.11 seconds (max_rss 23.6 MiB, delta_rss +0.7 MiB) -Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml +Command line to execute: build_fabric --compress_routing --duplicate_grid_pin --load_fabric_key /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml Confirm selected options when call command 'build_fabric': --frame_view: off --compress_routing: on --duplicate_grid_pin: on ---load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml +--load_fabric_key: /research/ece/lnis/USERS/DARPA_ERI/tools/OpenFPGA_for_Chip/openfpga_flow/tasks/FPGA1212_QLSOFA_HD_task/arch/fabric_key.xml --write_fabric_key: off --generate_random_fabric_key: off --verbose: off Identify unique General Switch Blocks (GSBs) Detected 9 unique general switch blocks from a total of 169 (compression rate=1777.78%) -Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.5 MiB, delta_rss +0.0 MiB) +Identify unique General Switch Blocks (GSBs) took 0.16 seconds (max_rss 23.6 MiB, delta_rss +0.0 MiB) Read Fabric Key Read Fabric Key took 0.00 seconds (max_rss 23.6 MiB, delta_rss +0.1 MiB) @@ -1157,7 +1123,7 @@ Build fabric module graph # Build wire modules # Build wire modules took 0.00 seconds (max_rss 23.9 MiB, delta_rss +0.0 MiB) # Build memory modules -# Build memory modules took 0.00 seconds (max_rss 24.1 MiB, delta_rss +0.3 MiB) +# Build memory modules took 0.00 seconds (max_rss 24.2 MiB, delta_rss +0.3 MiB) # Build grid modules Building logical tiles...Done Building physical tiles...Done @@ -1166,40 +1132,40 @@ Building physical tiles...Done # Build unique routing modules... took 0.02 seconds (max_rss 27.8 MiB, delta_rss +3.1 MiB) # Build FPGA fabric module ## Add grid instances to top module -## Add grid instances to top module took 0.00 seconds (max_rss 29.0 MiB, delta_rss +1.3 MiB) +## Add grid instances to top module took 0.00 seconds (max_rss 29.1 MiB, delta_rss +1.3 MiB) ## Add switch block instances to top module ## Add switch block instances to top module took 0.00 seconds (max_rss 29.8 MiB, delta_rss +0.8 MiB) ## Add connection block instances to top module ## Add connection block instances to top module took 0.00 seconds (max_rss 30.3 MiB, delta_rss +0.5 MiB) ## Add connection block instances to top module -## Add connection block instances to top module took 0.00 seconds (max_rss 30.8 MiB, delta_rss +0.5 MiB) +## Add connection block instances to top module took 0.00 seconds (max_rss 30.9 MiB, delta_rss +0.5 MiB) ## Add module nets between grids and GSBs -## Add module nets between grids and GSBs took 0.18 seconds (max_rss 52.2 MiB, delta_rss +21.4 MiB) +## Add module nets between grids and GSBs took 0.17 seconds (max_rss 52.3 MiB, delta_rss +21.4 MiB) ## Add module nets for inter-tile connections ## Add module nets for inter-tile connections took 0.00 seconds (max_rss 52.8 MiB, delta_rss +0.5 MiB) ## Add module nets for configuration buses -## Add module nets for configuration buses took 0.02 seconds (max_rss 54.6 MiB, delta_rss +1.5 MiB) -# Build FPGA fabric module took 0.22 seconds (max_rss 54.6 MiB, delta_rss +26.8 MiB) -Build fabric module graph took 0.24 seconds (max_rss 54.6 MiB, delta_rss +30.9 MiB) +## Add module nets for configuration buses took 0.02 seconds (max_rss 56.1 MiB, delta_rss +2.8 MiB) +# Build FPGA fabric module took 0.21 seconds (max_rss 56.1 MiB, delta_rss +28.3 MiB) +Build fabric module graph took 0.24 seconds (max_rss 56.1 MiB, delta_rss +32.4 MiB) Create I/O location mapping for top module -Create I/O location mapping for top module took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB) +Create I/O location mapping for top module took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB) Create global port info for top module -Create global port info for top module took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB) +Create global port info for top module took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB) Command line to execute: repack Confirm selected options when call command 'repack': --verbose: off Build routing resource graph for the physical implementation of logical tile -Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB) +Build routing resource graph for the physical implementation of logical tile took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB) Repack clustered blocks to physical implementation of logical tile Repack clustered block 'c'...Done Repack clustered block 'out:c'...Done Repack clustered block 'a'...Done Repack clustered block 'b'...Done -Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB) +Repack clustered blocks to physical implementation of logical tile took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB) Build truth tables for physical LUTs -Build truth tables for physical LUTs took 0.00 seconds (max_rss 54.6 MiB, delta_rss +0.0 MiB) +Build truth tables for physical LUTs took 0.00 seconds (max_rss 56.1 MiB, delta_rss +0.0 MiB) Command line to execute: build_architecture_bitstream --write_file fabric_indepenent_bitstream.xml @@ -1215,10 +1181,10 @@ Generating bitstream for X-direction Connection blocks ...Done Generating bitstream for Y-direction Connection blocks ...Done Build fabric-independent bitstream for implementation 'top' - took 0.18 seconds (max_rss 60.0 MiB, delta_rss +5.5 MiB) -Warning 185: Directory path is empty and nothing will be created. + took 0.16 seconds (max_rss 61.3 MiB, delta_rss +5.3 MiB) +Warning 151: Directory path is empty and nothing will be created. Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' -Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.54 seconds (max_rss 60.0 MiB, delta_rss +0.0 MiB) +Write 78765 architecture independent bitstream into XML file 'fabric_indepenent_bitstream.xml' took 0.53 seconds (max_rss 61.3 MiB, delta_rss +0.0 MiB) Command line to execute: build_fabric_bitstream @@ -1229,7 +1195,7 @@ Build fabric dependent bitstream Build fabric dependent bitstream - took 0.09 seconds (max_rss 64.9 MiB, delta_rss +4.9 MiB) + took 0.04 seconds (max_rss 66.2 MiB, delta_rss +4.9 MiB) Command line to execute: write_fabric_bitstream --format plain_text --file fabric_bitstream.bit @@ -1237,9 +1203,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.bit --format: plain_text --verbose: off -Warning 186: Directory path is empty and nothing will be created. +Warning 152: Directory path is empty and nothing will be created. Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit' -Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.02 seconds (max_rss 64.9 MiB, delta_rss +0.0 MiB) +Write 78765 fabric bitstream into plain text file 'fabric_bitstream.bit' took 0.02 seconds (max_rss 66.2 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_bitstream --format xml --file fabric_bitstream.xml @@ -1247,9 +1213,9 @@ Confirm selected options when call command 'write_fabric_bitstream': --file, -f: fabric_bitstream.xml --format: xml --verbose: off -Warning 187: Directory path is empty and nothing will be created. +Warning 153: Directory path is empty and nothing will be created. Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml' -Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.13 seconds (max_rss 65.0 MiB, delta_rss +0.1 MiB) +Write 78765 fabric bitstream into xml file 'fabric_bitstream.xml' took 0.10 seconds (max_rss 66.2 MiB, delta_rss +0.0 MiB) Command line to execute: write_fabric_verilog --file ./SRC --explicit_port_mapping --verbose @@ -1312,7 +1278,7 @@ Building physical tiles...Done Writing Verilog netlist for top-level module of FPGA fabric './SRC/fpga_top.v'...Done Written 71 Verilog modules in total Write Verilog netlists for FPGA fabric - took 0.52 seconds (max_rss 67.9 MiB, delta_rss +2.8 MiB) + took 0.42 seconds (max_rss 69.1 MiB, delta_rss +2.9 MiB) Command line to execute: write_verilog_testbench --file ./SRC --reference_benchmark_file_path top_output_verilog.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping @@ -1329,22 +1295,22 @@ Confirm selected options when call command 'write_verilog_testbench': --include_signal_init: off --support_icarus_simulator: off --verbose: off -Warning 188: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled +Warning 154: Forcely enable to print top-level Verilog netlist in formal verification purpose as print pre-configured top-level Verilog testbench is enabled Write Verilog testbenches for FPGA fabric -Warning 189: Directory './SRC' already exists. Will overwrite contents +Warning 155: Directory './SRC' already exists. Will overwrite contents # Write pre-configured FPGA top-level Verilog netlist for design 'top' -# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 2.73 seconds (max_rss 67.9 MiB, delta_rss +0.1 MiB) +# Write pre-configured FPGA top-level Verilog netlist for design 'top' took 2.65 seconds (max_rss 69.2 MiB, delta_rss +0.0 MiB) # Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' -# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 67.9 MiB, delta_rss +0.0 MiB) +# Write configuration-skip testbench for FPGA top-level Verilog netlist implemented by 'top' took 0.00 seconds (max_rss 69.2 MiB, delta_rss +0.0 MiB) # Write autocheck testbench for FPGA top-level Verilog netlist for 'top' Will use 78766 configuration clock cycles to top testbench -# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.20 seconds (max_rss 68.0 MiB, delta_rss +0.1 MiB) +# Write autocheck testbench for FPGA top-level Verilog netlist for 'top' took 0.14 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB) Succeed to create directory './SimulationDeck' # Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' -# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 68.0 MiB, delta_rss +0.0 MiB) +# Write exchangeable file containing simulation information './SimulationDeck/simulation_deck.ini' took 0.00 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB) Write Verilog testbenches for FPGA fabric - took 2.96 seconds (max_rss 68.0 MiB, delta_rss +0.1 MiB) + took 2.82 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB) Command line to execute: write_pnr_sdc --file ./SDC @@ -1366,19 +1332,19 @@ Confirm selected options when call command 'write_pnr_sdc': --verbose: off Succeed to create directory './SDC' Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' -Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 68.0 MiB, delta_rss +0.0 MiB) +Write SDC for constraining clocks for P&R flow './SDC/global_ports.sdc' took 0.00 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB) Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' -Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.00 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC to disable configurable memory outputs for P&R flow './SDC/disable_configurable_memory_outputs.sdc' took 0.01 seconds (max_rss 69.3 MiB, delta_rss +0.1 MiB) Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' -Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.03 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC to disable routing multiplexer outputs for P&R flow './SDC/disable_routing_multiplexer_outputs.sdc' took 0.04 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB) Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' -Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.00 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC to disable switch block outputs for P&R flow './SDC/disable_sb_outputs.sdc' took 0.02 seconds (max_rss 69.3 MiB, delta_rss +0.0 MiB) Write SDC for constrain Switch Block timing for P&R flow -Write SDC for constrain Switch Block timing for P&R flow took 0.03 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC for constrain Switch Block timing for P&R flow took 0.04 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB) Write SDC for constrain Connection Block timing for P&R flow -Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC for constrain Connection Block timing for P&R flow took 0.02 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB) Write SDC for constraining grid timing for P&R flow -Write SDC for constraining grid timing for P&R flow took 0.04 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC for constraining grid timing for P&R flow took 0.02 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB) Command line to execute: write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc @@ -1386,9 +1352,9 @@ Confirm selected options when call command 'write_sdc_disable_timing_configure_p --file, -f: ./SDC/disable_configure_ports.sdc --flatten_names: off --verbose: off -Warning 190: Directory './SDC' already exists. Will overwrite contents +Warning 156: Directory './SDC' already exists. Will overwrite contents Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' -Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.10 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Write SDC to disable timing on configuration outputs of programmable cells for P&R flow './SDC/disable_configure_ports.sdc' took 0.06 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB) Command line to execute: write_analysis_sdc --file ./SDC_analysis @@ -1399,7 +1365,7 @@ Confirm selected options when call command 'write_analysis_sdc': --time_unit: off Succeed to create directory './SDC_analysis' Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' -Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 1.06 seconds (max_rss 68.1 MiB, delta_rss +0.0 MiB) +Generating SDC for Timing/Power analysis on the mapped FPGA './SDC_analysis/top_fpga_top_analysis.sdc' took 0.85 seconds (max_rss 69.4 MiB, delta_rss +0.0 MiB) Command line to execute: exit @@ -1407,6 +1373,6 @@ Confirm selected options when call command 'exit': Finish execution with 0 errors -The entire OpenFPGA flow took 6.57 seconds +The entire OpenFPGA flow took 5.93 seconds Thank you for using OpenFPGA! diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/proj_const.tcl b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/proj_const.tcl index d14cabd..48f0cb6 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/proj_const.tcl +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/proj_const.tcl @@ -2,6 +2,7 @@ set DIE_HEIGHT 3200 set DIE_WIDTH 3200 set DESIGN_NAME fpga_core set TASK_NAME FPGA1212_QLSOFA_HD_task +set PROJ_NAME FPGA1212_QLSOFA_HD set VERILOG_PROJ_DIR FPGA1212_QLSOFA_HD_Verilog set FPGA_ROW 12 set FPGA_COL 12 diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__0__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__0__scandef.def index e69de29..f7b3acb 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__0__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__0__scandef.def @@ -0,0 +1,36 @@ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__1__scandef.def index e69de29..8369ca0 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__1__scandef.def @@ -0,0 +1,64 @@ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__2__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__2__scandef.def index e69de29..8369ca0 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__2__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cbx_1__2__scandef.def @@ -0,0 +1,64 @@ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_0__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_0__1__scandef.def index e69de29..b83b622 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_0__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_0__1__scandef.def @@ -0,0 +1,4 @@ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_1__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_1__1__scandef.def index e69de29..e403479 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_1__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_1__1__scandef.def @@ -0,0 +1,64 @@ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_2__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_2__1__scandef.def index e69de29..e403479 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_2__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/cby_2__1__scandef.def @@ -0,0 +1,64 @@ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_8/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_9/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_14/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_ipin_15/sky130_fd_sc_hd__dfxtp_1_3_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/grid_clb_scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/grid_clb_scandef.def index e69de29..471aed9 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/grid_clb_scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/grid_clb_scandef.def @@ -0,0 +1,1232 @@ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_1/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_2/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_3/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_4/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_5/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_6/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_2_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_3_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_4_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_5_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_6_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_7_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_8_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/sky130_fd_sc_hd__dfxtp_1_9_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[10] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[11] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[12] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[13] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[14] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[15] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0/frac_lut4_sky130_fd_sc_hd__dfrtp_1_mem/mem_out[16] +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_logic_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0/mem_frac_lut4_0_in_2/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_fabric_out_1/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_0_D_0/sky130_fd_sc_hd__dfxtp_1_1_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_0_ +logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/mem_ff_1_D_0/sky130_fd_sc_hd__dfxtp_1_1_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__0__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__0__scandef.def index e69de29..02186dd 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__0__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__0__scandef.def @@ -0,0 +1,76 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_42/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_42/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_58/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_58/sky130_fd_sc_hd__dfxtp_1_1_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__1__scandef.def index e69de29..08edd64 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__1__scandef.def @@ -0,0 +1,132 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__2__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__2__scandef.def index e69de29..08edd64 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__2__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_0__2__scandef.def @@ -0,0 +1,132 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_16/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_18/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_22/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_24/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_26/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_30/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_32/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_34/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_38/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_40/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_46/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_48/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_50/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_54/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_56/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__0__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__0__scandef.def index e69de29..415a359 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__0__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__0__scandef.def @@ -0,0 +1,135 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__1__scandef.def index e69de29..664caf9 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__1__scandef.def @@ -0,0 +1,164 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__2__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__2__scandef.def index e69de29..664caf9 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__2__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_1__2__scandef.def @@ -0,0 +1,164 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__0__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__0__scandef.def index e69de29..415a359 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__0__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__0__scandef.def @@ -0,0 +1,135 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_8/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_14/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_16/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_18/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_22/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_24/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_26/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_30/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_32/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_34/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_40/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_42/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_46/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_48/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_50/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_58/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__1__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__1__scandef.def index e69de29..664caf9 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__1__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__1__scandef.def @@ -0,0 +1,164 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__2__scandef.def b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__2__scandef.def index e69de29..664caf9 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__2__scandef.def +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/scandef/sb_2__2__scandef.def @@ -0,0 +1,164 @@ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_top_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_0/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_2/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_4/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_6/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_10/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_12/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_20/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_28/sky130_fd_sc_hd__dfxtp_1_3_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_36/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_44/sky130_fd_sc_hd__dfxtp_1_2_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_0_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_1_ +mem_right_track_52/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_bottom_track_53/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_1/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_3/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_5/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_7/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_11/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_13/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_21/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_29/sky130_fd_sc_hd__dfxtp_1_3_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_37/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_45/sky130_fd_sc_hd__dfxtp_1_2_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_0_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_1_ +mem_left_track_53/sky130_fd_sc_hd__dfxtp_1_2_ diff --git a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml index 9460738..cb96924 100644 --- a/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml +++ b/FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/arch/vpr_arch.xml @@ -447,10 +447,12 @@ - - - - + + + + + + diff --git a/FPGA1212_QLSOFA_HD_PNR/config.sh b/FPGA1212_QLSOFA_HD_PNR/config.sh index 447cfb2..3253ebc 100644 --- a/FPGA1212_QLSOFA_HD_PNR/config.sh +++ b/FPGA1212_QLSOFA_HD_PNR/config.sh @@ -24,7 +24,7 @@ export DIE_DIMENSION=3200 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = # Derived Or Fixed Variables # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -export OPENFPGA_ENGINE_PATH=/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/OpenFPGA_for_Chip +export OPENFPGA_ENGINE_PATH=${OPENFPGA_PATH} export TASK_DIR_NAME=${PROJ_NAME}_task export VERILOG_PROJ_DIR=${PROJ_NAME}_Verilog export SPY_HACK_FILE=${TASK_DIR_NAME}/spy_hack.txt diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png index 6d5ec63..8be0ff4 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigFlipFLop.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png index 650f063..031fbe5 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ConfigurationChain.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png index 3403ab8..dca0003 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/ProgClockTree.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/clockTree.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/clockTree.png index 980e224..8dec5d5 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/clockTree.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/clockTree.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png index 4800d9a..be19a2a 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met1_utilization.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png index 66c71e0..53b244d 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met2_utilization.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png index 841ad2f..991119e 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met3_utilization.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png index 07b8479..9f051a2 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/met4_utilization.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png index 2a601cb..e02bad5 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/power_contacts.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/utilization.png b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/utilization.png index 9b495ba..8e30834 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/utilization.png and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/Screenshots/utilization.png differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v index 84c3355..eb42046 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.fm.v @@ -39958,18 +39958,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_198 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , - .X ( copt_net_196 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( copt_net_197 ) , .X ( copt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_200 ) , .X ( copt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_201 ) , .X ( copt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1642 ( .A ( mem_out[1] ) , + .X ( copt_net_201 ) ) ; endmodule @@ -40089,11 +40089,11 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_521_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_132 ) ) ; + .X ( aps_rename_522_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_522_ ) , + .Y ( BUF_net_131 ) ) ; endmodule @@ -40119,11 +40119,11 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_129 ) ) ; + .X ( aps_rename_521_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -40140,12 +40140,10 @@ output p_abuf1 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_84 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -40248,8 +40246,11 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb22 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( X ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_133 ) ) ; endmodule @@ -40263,7 +40264,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -40491,20 +40492,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -40521,7 +40522,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf2 , p_abuf3 , p0 , p1 ) ; + p_abuf2 , p_abuf3 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40541,12 +40542,10 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; -input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -40559,14 +40558,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -40583,21 +40580,21 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2 mux_ff_1_D_0 ( .in ( { @@ -40605,8 +40602,8 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -40631,7 +40628,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -40651,19 +40648,17 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; input p0 ; -input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; endmodule @@ -40759,12 +40754,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -40772,7 +40767,7 @@ grid_clb_const1_40 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -40800,10 +40795,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) ) ; endmodule @@ -40830,10 +40825,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -40951,8 +40946,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb19 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -40966,7 +40960,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -41195,20 +41189,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41225,7 +41219,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p1 , p3 ) ; + p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -41244,13 +41238,11 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -41263,14 +41255,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) , .p3 ( p3 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -41287,29 +41277,29 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41335,7 +41325,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -41354,20 +41344,17 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -41504,10 +41491,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -41534,10 +41521,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -41655,8 +41642,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb16 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -41670,7 +41656,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -41898,20 +41884,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41951,7 +41937,6 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -41964,12 +41949,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -41988,21 +41971,21 @@ grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { @@ -42010,7 +41993,7 @@ grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -42059,14 +42042,12 @@ input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; endmodule @@ -42162,12 +42143,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42175,7 +42156,7 @@ grid_clb_const1_28 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -42203,10 +42184,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -42233,10 +42214,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -42330,12 +42311,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -42343,7 +42324,7 @@ grid_clb_const1_24 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -42354,8 +42335,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb13 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -42369,7 +42349,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -42561,7 +42541,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -42571,6 +42551,7 @@ output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input p2 ; +input p3 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -42597,20 +42578,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -42627,7 +42608,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p2 , p3 ) ; + p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -42645,13 +42626,13 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -42664,14 +42645,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p2 ( p2 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -42688,29 +42667,29 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -42736,7 +42715,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -42754,20 +42733,20 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , + .p3 ( p3 ) ) ; endmodule @@ -42904,10 +42883,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -42934,10 +42913,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) ) ; endmodule @@ -43055,8 +43034,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb10 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -43070,7 +43048,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -43298,20 +43276,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -43351,7 +43329,6 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -43364,12 +43341,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -43388,21 +43363,21 @@ grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( .in ( { @@ -43410,7 +43385,7 @@ grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -43459,14 +43434,12 @@ input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -43562,12 +43535,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -43575,7 +43548,7 @@ grid_clb_const1_16 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -43603,10 +43576,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -43633,10 +43606,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -43754,8 +43727,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb7 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -43769,7 +43741,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -43997,20 +43969,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -44052,7 +44024,6 @@ input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -44065,12 +44036,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -44089,29 +44058,29 @@ grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -44162,14 +44131,13 @@ input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , + .p4 ( p4 ) ) ; endmodule @@ -44305,10 +44273,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -44334,10 +44302,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -44455,8 +44423,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb4 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -44470,7 +44437,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -44698,20 +44665,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -44752,7 +44719,6 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -44765,12 +44731,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -44789,21 +44753,21 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { @@ -44811,7 +44775,7 @@ grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -44861,14 +44825,12 @@ input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -44941,12 +44903,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -44954,7 +44916,7 @@ grid_clb_const1_5 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -44964,12 +44926,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -44977,7 +44939,7 @@ grid_clb_const1_4 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -45004,10 +44966,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -45033,10 +44995,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -45130,12 +45092,12 @@ output [0:0] const1 ; endmodule -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; @@ -45143,7 +45105,7 @@ grid_clb_const1_0 const1_0_ ( .const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -45154,8 +45116,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb1 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -45169,7 +45130,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -45181,7 +45142,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_203 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -45216,20 +45177,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , - .X ( copt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( ccff_head[0] ) , .X ( copt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_195 ) , .X ( copt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_191 ) , .X ( copt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_190 ) , .X ( copt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_192 ) , .X ( copt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , - .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1636 ( .A ( copt_net_193 ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1644 ( .A ( copt_net_194 ) , + .X ( ropt_net_203 ) ) ; endmodule @@ -45375,7 +45336,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p1 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -45384,7 +45345,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p1 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -45412,20 +45372,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -45442,7 +45402,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p4 ) ; + p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -45460,13 +45420,13 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -45479,14 +45439,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) , .p4 ( p4 ) ) ; + .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -45503,30 +45461,30 @@ grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -45551,7 +45509,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -45569,20 +45527,20 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p4 ( p4 ) ) ; endmodule @@ -45649,12 +45607,19 @@ input p4 ; input p5 ; wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_34_out ; wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_43_out ; wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_52_out ; wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_61_out ; wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_70_out ; wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_79_out ; wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_88_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; @@ -45673,42 +45638,42 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , - .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_reg_out ( direct_interc_32_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( direct_interc_34_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p2 ) , + .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , .fle_reg_in ( direct_interc_32_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_reg_out ( direct_interc_41_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( direct_interc_43_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , .fle_reg_in ( direct_interc_41_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_reg_out ( direct_interc_50_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( direct_interc_52_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; @@ -45716,71 +45681,71 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , .fle_reg_in ( direct_interc_50_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_reg_out ( direct_interc_59_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( direct_interc_61_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , .fle_reg_in ( direct_interc_59_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_reg_out ( direct_interc_68_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( direct_interc_70_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , + .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , .fle_reg_in ( direct_interc_68_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_reg_out ( direct_interc_77_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( direct_interc_79_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , .fle_reg_in ( direct_interc_77_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_reg_out ( direct_interc_86_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( direct_interc_88_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , - .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , .fle_reg_in ( direct_interc_86_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) ) ; endmodule @@ -45984,17 +45949,17 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( right_width_0_height_0__pin_31_[0] } ) , .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , - .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , - aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , - aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , - aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , - right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , - aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , - aps_rename_537_ } ) , + .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) , + .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_523_ , aps_rename_524_ , aps_rename_525_ , + aps_rename_526_ , aps_rename_527_ , aps_rename_528_ , + aps_rename_529_ , aps_rename_530_ , aps_rename_531_ , + aps_rename_532_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_535_ , + aps_rename_536_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_538_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_538_ } ) , + .clb_sc_out ( { aps_rename_539_ } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , @@ -46011,98 +45976,98 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , - .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , - .p5 ( optlc_net_184 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_180 ) , .p1 ( optlc_net_181 ) , + .p2 ( optlc_net_182 ) , .p3 ( optlc_net_183 ) , .p4 ( optlc_net_184 ) , + .p5 ( optlc_net_185 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( aps_rename_539_ ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_540_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_541_ ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_541_ ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , .X ( aps_rename_542_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_543_ ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1185 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2186 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3187 ) ) ; + .X ( ctsbuf_net_1186 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2187 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3188 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4188 ) ) ; + .X ( ctsbuf_net_4189 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_523_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_524_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_525_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_526_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_527_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_528_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_529_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_530_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_531_ ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_535_ ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_536_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_538_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_539_ ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_134 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_136 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_138 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_179 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_542_ ) , + .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_181 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_543_ ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981326 ( .A ( ctsbuf_net_1186 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031331 ( .A ( ctsbuf_net_2187 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4081336 ( .A ( ctsbuf_net_3188 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131341 ( .A ( ctsbuf_net_4189 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz index 7edf133..1b659cd 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.gds.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v index c372496..dd79e73 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -46042,18 +46042,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_198 ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , - .X ( copt_net_196 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( copt_net_197 ) , .X ( copt_net_198 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_200 ) , .X ( copt_net_199 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_201 ) , .X ( copt_net_200 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1642 ( .A ( mem_out[1] ) , + .X ( copt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46194,13 +46194,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) , + .X ( aps_rename_522_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_132 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_522_ ) , + .Y ( BUF_net_131 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46224,13 +46224,13 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_520_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) , + .X ( aps_rename_521_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_129 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_128 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46253,16 +46253,14 @@ supply0 VSS ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) , .VPWR ( VDD ) , + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) , +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) , +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_84 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46393,8 +46391,12 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb22 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( aps_rename_519_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_133 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -46413,7 +46415,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -46695,21 +46697,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -46727,7 +46728,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf2 , p_abuf3 , p0 , p1 ) ; + p_abuf0 , p_abuf2 , p_abuf3 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -46749,12 +46750,10 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; -input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -46769,14 +46768,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -46794,23 +46791,23 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2 mux_ff_1_D_0 ( .in ( { @@ -46818,8 +46815,8 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -46845,7 +46842,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -46867,7 +46864,6 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; input p0 ; -input p1 ; supply1 VDD ; supply0 VSS ; @@ -46875,14 +46871,13 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , - .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p_abuf3 ( p_abuf2 ) , .p0 ( p0 ) ) ; endmodule @@ -47006,14 +47001,14 @@ endmodule module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , VDD , VSS , - p0 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -47022,7 +47017,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47049,12 +47044,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47079,12 +47074,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47236,8 +47231,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb19 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47256,7 +47251,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -47539,21 +47534,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -47571,7 +47565,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; + p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -47592,13 +47586,11 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -47613,14 +47605,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p1 ) , .p3 ( p3 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -47637,31 +47627,31 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -47688,7 +47678,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -47709,7 +47699,6 @@ input VSS ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; supply1 VDD ; @@ -47718,14 +47707,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -47893,12 +47880,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -47923,12 +47910,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48080,8 +48067,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb16 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48100,7 +48087,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -48382,21 +48369,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -48439,7 +48425,6 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -48454,12 +48439,10 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -48478,7 +48461,7 @@ grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( @@ -48486,7 +48469,7 @@ grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( @@ -48494,7 +48477,7 @@ grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { @@ -48502,7 +48485,7 @@ grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -48557,14 +48540,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; endmodule @@ -48688,14 +48669,14 @@ endmodule module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48704,7 +48685,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48731,12 +48712,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48761,12 +48742,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_111 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48884,14 +48865,14 @@ endmodule module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -48900,7 +48881,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48918,8 +48899,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb13 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -48938,7 +48919,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -49179,7 +49160,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -49191,6 +49172,7 @@ output [0:0] ccff_tail ; input VDD ; input VSS ; input p2 ; +input p3 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -49220,21 +49202,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -49252,7 +49233,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p2 , p3 ) ; + p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -49272,13 +49253,13 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -49293,14 +49274,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -49317,7 +49296,7 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( @@ -49325,7 +49304,7 @@ grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( @@ -49333,15 +49312,15 @@ grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -49368,7 +49347,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -49388,6 +49367,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; @@ -49397,14 +49377,13 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , + .p2 ( p2 ) , .p3 ( p3 ) ) ; endmodule @@ -49571,12 +49550,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_108 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49601,12 +49580,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49758,8 +49737,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb10 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -49778,7 +49757,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -50060,21 +50039,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -50117,7 +50095,6 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -50132,12 +50109,10 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -50156,7 +50131,7 @@ grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( @@ -50164,7 +50139,7 @@ grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( @@ -50172,7 +50147,7 @@ grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( .in ( { @@ -50180,7 +50155,7 @@ grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -50235,14 +50210,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -50366,14 +50339,14 @@ endmodule module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , VDD , VSS , - p2 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -50382,7 +50355,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50409,12 +50382,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_102 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50439,12 +50412,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_99 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50596,8 +50569,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb7 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -50616,7 +50589,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -50898,21 +50871,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -50957,7 +50929,6 @@ input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -50972,12 +50943,10 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -50996,7 +50965,7 @@ grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( @@ -51004,7 +50973,7 @@ grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( @@ -51012,15 +50981,15 @@ grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -51077,15 +51046,13 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , - .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , + .p2 ( p2 ) , .p4 ( p4 ) ) ; endmodule @@ -51252,12 +51219,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_96 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51282,12 +51249,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_93 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51439,8 +51406,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb4 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -51459,7 +51426,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -51741,21 +51708,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -51799,7 +51765,6 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -51814,12 +51779,10 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -51838,7 +51801,7 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( @@ -51846,7 +51809,7 @@ grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( @@ -51854,7 +51817,7 @@ grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { @@ -51862,7 +51825,7 @@ grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -51918,14 +51881,13 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , + .p1 ( p1 ) ) ; endmodule @@ -52026,14 +51988,14 @@ endmodule module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -52042,21 +52004,21 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -52065,7 +52027,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52092,12 +52054,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52122,12 +52084,12 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) , +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) , +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_87 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52245,14 +52207,14 @@ endmodule module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , VDD , VSS , - p1 ) ; + p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; input VDD ; input VSS ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; supply1 VDD ; @@ -52261,7 +52223,7 @@ supply0 VSS ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52279,8 +52241,8 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb1 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) , + .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52299,7 +52261,7 @@ supply0 VSS ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) , + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; endmodule @@ -52317,7 +52279,7 @@ input VSS ; supply1 VDD ; supply0 VSS ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_203 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , @@ -52370,20 +52332,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , - .X ( copt_net_189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( ccff_head[0] ) , .X ( copt_net_190 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_195 ) , .X ( copt_net_191 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_191 ) , .X ( copt_net_192 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_190 ) , .X ( copt_net_193 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_192 ) , .X ( copt_net_194 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , - .X ( ropt_net_201 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1636 ( .A ( copt_net_193 ) , + .X ( copt_net_195 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1644 ( .A ( copt_net_194 ) , + .X ( ropt_net_203 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule @@ -52554,7 +52516,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p1 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , VDD , VSS , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -52565,7 +52527,6 @@ output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input VDD ; input VSS ; -input p1 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -52596,21 +52557,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - .VDD ( VDD ) , .VSS ( VSS ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) , .VDD ( VDD ) , .VSS ( VSS ) ) ; grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -52628,7 +52588,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , VDD , VSS , - p_abuf0 , p_abuf1 , p1 , p4 ) ; + p_abuf0 , p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -52648,13 +52608,13 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -52669,14 +52629,12 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; + .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -52693,7 +52651,7 @@ grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( @@ -52701,7 +52659,7 @@ grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( @@ -52709,16 +52667,16 @@ grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .VDD ( VDD ) , .VSS ( VSS ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -52744,7 +52702,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p1 , p4 ) ; + ccff_tail , VDD , VSS , p_abuf0 , p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -52764,6 +52722,7 @@ input VDD ; input VSS ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; @@ -52773,14 +52732,13 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , - .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p1 ( p1 ) , .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , + .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , + .p1 ( p1 ) , .p4 ( p4 ) ) ; endmodule @@ -52850,12 +52808,19 @@ input p4 ; input p5 ; wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_34_out ; wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_43_out ; wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_52_out ; wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_61_out ; wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_70_out ; wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_79_out ; wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_88_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; @@ -52876,29 +52841,28 @@ supply0 VSS ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , - .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_reg_out ( direct_interc_32_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( direct_interc_34_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf1 ) , - .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , .fle_reg_in ( direct_interc_32_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_reg_out ( direct_interc_41_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( direct_interc_43_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; @@ -52906,14 +52870,14 @@ grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , .fle_reg_in ( direct_interc_41_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_reg_out ( direct_interc_50_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( direct_interc_52_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; @@ -52921,14 +52885,14 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , .fle_reg_in ( direct_interc_50_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_reg_out ( direct_interc_59_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( direct_interc_61_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; @@ -52936,29 +52900,29 @@ grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , .fle_reg_in ( direct_interc_59_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_reg_out ( direct_interc_68_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( direct_interc_70_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf9 ) , - .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , .fle_reg_in ( direct_interc_68_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_reg_out ( direct_interc_77_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( direct_interc_79_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; @@ -52966,30 +52930,30 @@ grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , .fle_reg_in ( direct_interc_77_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_reg_out ( direct_interc_86_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( direct_interc_88_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf13 ) , - .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p4 ) ) ; + .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , .fle_reg_in ( direct_interc_86_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf15 ) , - .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) ) ; endmodule @@ -53198,17 +53162,17 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( right_width_0_height_0__pin_31_[0] } ) , .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , - .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , - aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , - aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , - aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , - right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , - aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , - aps_rename_537_ } ) , + .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) , + .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_523_ , aps_rename_524_ , aps_rename_525_ , + aps_rename_526_ , aps_rename_527_ , aps_rename_528_ , + aps_rename_529_ , aps_rename_530_ , aps_rename_531_ , + aps_rename_532_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_535_ , + aps_rename_536_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_538_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_538_ } ) , + .clb_sc_out ( { aps_rename_539_ } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) , .p_abuf0 ( SC_OUT_BOT ) , @@ -53226,63 +53190,63 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , - .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , - .p5 ( optlc_net_184 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_180 ) , .p1 ( optlc_net_181 ) , + .p2 ( optlc_net_182 ) , .p3 ( optlc_net_183 ) , .p4 ( optlc_net_184 ) , + .p5 ( optlc_net_185 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( aps_rename_539_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_540_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_541_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_541_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , .X ( aps_rename_542_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_543_ ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_1186 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2187 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4188 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; + .X ( ctsbuf_net_4189 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_523_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_524_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_525_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_526_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_527_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_528_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_529_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_530_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_531_ ) , .X ( right_width_0_height_0__pin_44_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , @@ -53291,53 +53255,53 @@ sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_535_ ) , .X ( right_width_0_height_0__pin_48_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_536_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_538_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_539_ ) , .X ( SC_OUT_TOP ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( Test_en_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_134 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Test_en_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) , +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( Reset_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_138 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_179 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_542_ ) , + .Y ( BUF_net_139 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_180 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_181 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_182 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_183 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_184 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_185 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_543_ ) , .X ( Reset_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981326 ( .A ( ctsbuf_net_1186 ) , .X ( prog_clk_0_S_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031331 ( .A ( ctsbuf_net_2187 ) , .X ( prog_clk_0_E_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4081336 ( .A ( ctsbuf_net_3188 ) , .X ( prog_clk_0_W_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131341 ( .A ( ctsbuf_net_4189 ) , .X ( prog_clk_0_N_out ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ; endmodule diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz index 19d50bf..e8835f3 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz and b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.nominal_25.spef.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v index daadd83..2939dc4 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v @@ -36521,18 +36521,18 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_196 ) , +sky130_fd_sc_hd__buf_6 FTB_63__62 ( .A ( copt_net_198 ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1637 ( .A ( copt_net_200 ) , - .X ( copt_net_196 ) ) ; sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1638 ( .A ( copt_net_199 ) , .X ( copt_net_197 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( mem_out[1] ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1639 ( .A ( copt_net_197 ) , .X ( copt_net_198 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_198 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1640 ( .A ( copt_net_200 ) , .X ( copt_net_199 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_197 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1641 ( .A ( copt_net_201 ) , .X ( copt_net_200 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1642 ( .A ( mem_out[1] ) , + .X ( copt_net_201 ) ) ; endmodule @@ -36631,11 +36631,11 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_521_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_130 ( .A ( BUF_net_132 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_131 ( .A ( BUF_net_132 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_132 ( .A ( aps_rename_521_ ) , - .Y ( BUF_net_132 ) ) ; + .X ( aps_rename_522_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_129 ( .A ( BUF_net_131 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_130 ( .A ( BUF_net_131 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_131 ( .A ( aps_rename_522_ ) , + .Y ( BUF_net_131 ) ) ; endmodule @@ -36654,11 +36654,11 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , - .X ( aps_rename_520_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_127 ( .A ( BUF_net_129 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_128 ( .A ( BUF_net_129 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_129 ( .A ( aps_rename_520_ ) , - .Y ( BUF_net_129 ) ) ; + .X ( aps_rename_521_ ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_126 ( .A ( BUF_net_128 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_127 ( .A ( BUF_net_128 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_128 ( .A ( aps_rename_521_ ) , + .Y ( BUF_net_128 ) ) ; endmodule @@ -36675,12 +36675,10 @@ output p_abuf1 ; sky130_fd_sc_hd__sdfrtp_1 sky130_fd_sc_hd__sdfrtp_1_0_ ( .D ( ff_D[0] ) , .SCD ( ff_DI[0] ) , .SCE ( Test_en[0] ) , .CLK ( ff_clk[0] ) , - .RESET_B ( ff_reset[0] ) , .Q ( aps_rename_519_ ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_84 ) , .Y ( ff_Q[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_84 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( BUF_net_84 ) , .Y ( p_abuf1 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_84 ( .A ( aps_rename_519_ ) , - .Y ( BUF_net_84 ) ) ; + .RESET_B ( ff_reset[0] ) , .Q ( p_abuf1 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_81 ( .A ( BUF_net_83 ) , .Y ( ff_Q[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_82 ( .A ( BUF_net_83 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_83 ( .A ( p_abuf1 ) , .Y ( BUF_net_83 ) ) ; endmodule @@ -36769,8 +36767,11 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb22 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , + .X ( aps_rename_519_ ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_132 ( .A ( BUF_net_133 ) , .Y ( X ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_133 ( .A ( aps_rename_519_ ) , + .Y ( BUF_net_133 ) ) ; endmodule @@ -36784,7 +36785,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -37012,20 +37013,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_42 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_43 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_42 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -37042,7 +37043,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf2 , p_abuf3 , p0 , p1 ) ; + p_abuf2 , p_abuf3 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37062,12 +37063,10 @@ output p_abuf0 ; output p_abuf2 ; output p_abuf3 ; input p0 ; -input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -37080,14 +37079,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) ) ; + .p0 ( p0 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_14 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -37104,21 +37101,21 @@ grid_clb_mux_tree_size2_44 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf2 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_45 mux_fabric_out_1 ( .in ( { p_abuf1 , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf3 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_46 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2 mux_ff_1_D_0 ( .in ( { @@ -37126,8 +37123,8 @@ grid_clb_mux_tree_size2 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_44 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -37152,7 +37149,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 , p1 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p_abuf2 , p0 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37172,19 +37169,17 @@ output p_abuf0 ; output p_abuf1 ; output p_abuf2 ; input p0 ; -input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf2 ( p_abuf1 ) , .p_abuf3 ( p_abuf2 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p0 ( p0 ) ) ; endmodule @@ -37268,18 +37263,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , endmodule -module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p0 ) ; +module grid_clb_mux_tree_size2_40 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p0 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -37300,10 +37295,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_518_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_124 ( .A ( BUF_net_126 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( aps_rename_518_ ) , - .Y ( BUF_net_126 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_123 ( .A ( BUF_net_125 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_124 ( .A ( BUF_net_125 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_125 ( .A ( aps_rename_518_ ) , + .Y ( BUF_net_125 ) ) ; endmodule @@ -37323,10 +37318,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_517_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_121 ( .A ( BUF_net_123 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_122 ( .A ( BUF_net_123 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_123 ( .A ( aps_rename_517_ ) , - .Y ( BUF_net_123 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_120 ( .A ( BUF_net_122 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_121 ( .A ( BUF_net_122 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_122 ( .A ( aps_rename_517_ ) , + .Y ( BUF_net_122 ) ) ; endmodule @@ -37430,8 +37425,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb19 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -37445,7 +37439,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_6 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -37674,20 +37668,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_36 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_37 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_36 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -37704,7 +37698,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p0 , p1 , p3 ) ; + p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37723,13 +37717,11 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -37742,14 +37734,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p0 ( p1 ) , .p3 ( p3 ) ) ; + .p0 ( p0 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_12 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -37766,29 +37756,29 @@ grid_clb_mux_tree_size2_38 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_39 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , - .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , + .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_40 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_41 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_38 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -37814,7 +37804,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_6 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -37833,20 +37823,17 @@ output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; input p0 ; -input p1 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p1 ( p1 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p3 ( p3 ) ) ; endmodule @@ -37962,10 +37949,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_516_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_118 ( .A ( BUF_net_120 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_119 ( .A ( BUF_net_120 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_120 ( .A ( aps_rename_516_ ) , - .Y ( BUF_net_120 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_117 ( .A ( BUF_net_119 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_118 ( .A ( BUF_net_119 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_119 ( .A ( aps_rename_516_ ) , + .Y ( BUF_net_119 ) ) ; endmodule @@ -37985,10 +37972,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_515_ ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_115 ( .A ( BUF_net_117 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_116 ( .A ( BUF_net_117 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_117 ( .A ( aps_rename_515_ ) , - .Y ( BUF_net_117 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_114 ( .A ( BUF_net_116 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_115 ( .A ( BUF_net_116 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_116 ( .A ( aps_rename_515_ ) , + .Y ( BUF_net_116 ) ) ; endmodule @@ -38092,8 +38079,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb16 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -38107,7 +38093,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_5 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -38335,20 +38321,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_30 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_31 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_30 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -38388,7 +38374,6 @@ input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -38401,12 +38386,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_10 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -38425,21 +38408,21 @@ grid_clb_mux_tree_size2_32 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_33 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_34 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( .in ( { @@ -38447,7 +38430,7 @@ grid_clb_mux_tree_size2_35 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_32 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -38496,14 +38479,12 @@ input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_5 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p3 ( p3 ) ) ; endmodule @@ -38587,18 +38568,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , endmodule -module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_28 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -38619,10 +38600,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_514_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_112 ( .A ( BUF_net_114 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_113 ( .A ( BUF_net_114 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_114 ( .A ( aps_rename_514_ ) , - .Y ( BUF_net_114 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_111 ( .A ( BUF_net_113 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_112 ( .A ( BUF_net_113 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_113 ( .A ( aps_rename_514_ ) , + .Y ( BUF_net_113 ) ) ; endmodule @@ -38642,10 +38623,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_513_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_109 ( .A ( BUF_net_111 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_110 ( .A ( BUF_net_111 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_111 ( .A ( aps_rename_513_ ) , - .Y ( BUF_net_111 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_108 ( .A ( BUF_net_110 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_109 ( .A ( BUF_net_110 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_110 ( .A ( aps_rename_513_ ) , + .Y ( BUF_net_110 ) ) ; endmodule @@ -38727,18 +38708,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_24 ( in , sram , sram_inv , out , p3 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p3 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p3 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -38749,8 +38730,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb13 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -38764,7 +38744,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_4 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -38956,7 +38936,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p2 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -38966,6 +38946,7 @@ output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; input p2 ; +input p3 ; wire [0:0] direct_interc_5_out ; wire [0:0] direct_interc_7_out ; @@ -38992,20 +38973,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_24 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_25 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_24 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -39022,7 +39003,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p2 , p3 ) ; + p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -39040,13 +39021,13 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -39059,14 +39040,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p2 ( p2 ) ) ; + .p2 ( p2 ) , .p3 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_8 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -39083,29 +39062,29 @@ grid_clb_mux_tree_size2_26 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_27 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_28 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_29 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p3 ( p3 ) ) ; grid_clb_mux_tree_size2_mem_26 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -39131,7 +39110,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_4 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p2 , p3 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p2 , p3 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -39149,20 +39128,20 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p2 ; input p3 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) , .p3 ( p3 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , + .p3 ( p3 ) ) ; endmodule @@ -39278,10 +39257,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_512_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_106 ( .A ( BUF_net_108 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_107 ( .A ( BUF_net_108 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_108 ( .A ( aps_rename_512_ ) , - .Y ( BUF_net_108 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_105 ( .A ( BUF_net_107 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_106 ( .A ( BUF_net_107 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_107 ( .A ( aps_rename_512_ ) , + .Y ( BUF_net_107 ) ) ; endmodule @@ -39301,10 +39280,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_511_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_103 ( .A ( BUF_net_105 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_104 ( .A ( BUF_net_105 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_105 ( .A ( aps_rename_511_ ) , - .Y ( BUF_net_105 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_102 ( .A ( BUF_net_104 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_103 ( .A ( BUF_net_104 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_104 ( .A ( aps_rename_511_ ) , + .Y ( BUF_net_104 ) ) ; endmodule @@ -39408,8 +39387,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb10 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -39423,7 +39401,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_3 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -39651,20 +39629,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_18 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_19 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_18 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -39704,7 +39682,6 @@ input p2 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -39717,12 +39694,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p2 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_6 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -39741,21 +39716,21 @@ grid_clb_mux_tree_size2_20 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_21 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_22 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( .in ( { @@ -39763,7 +39738,7 @@ grid_clb_mux_tree_size2_23 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_20 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -39812,14 +39787,12 @@ input p2 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_3 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p2 ( p2 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p2 ( p2 ) ) ; endmodule @@ -39903,18 +39876,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , endmodule -module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p2 ) ; +module grid_clb_mux_tree_size2_16 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p2 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p2 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -39935,10 +39908,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_510_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_100 ( .A ( BUF_net_102 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_101 ( .A ( BUF_net_102 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_510_ ) , - .Y ( BUF_net_102 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_99 ( .A ( BUF_net_101 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_100 ( .A ( BUF_net_101 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_101 ( .A ( aps_rename_510_ ) , + .Y ( BUF_net_101 ) ) ; endmodule @@ -39958,10 +39931,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_509_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_97 ( .A ( BUF_net_99 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_98 ( .A ( BUF_net_99 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_99 ( .A ( aps_rename_509_ ) , - .Y ( BUF_net_99 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_96 ( .A ( BUF_net_98 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_509_ ) , + .Y ( BUF_net_98 ) ) ; endmodule @@ -40065,8 +40038,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb7 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -40080,7 +40052,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_2 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -40308,20 +40280,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_12 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_13 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_12 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -40363,7 +40335,6 @@ input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -40376,12 +40347,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_4 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -40400,29 +40369,29 @@ grid_clb_mux_tree_size2_14 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_15 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_16 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p2 ( p2 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_17 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p2 ( p2 ) ) ; grid_clb_mux_tree_size2_mem_14 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -40473,14 +40442,13 @@ input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p2 ( p2 ) , .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p2 ( p2 ) , + .p4 ( p4 ) ) ; endmodule @@ -40595,10 +40563,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_508_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_94 ( .A ( BUF_net_96 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_508_ ) , - .Y ( BUF_net_96 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_93 ( .A ( BUF_net_95 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_94 ( .A ( BUF_net_95 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_95 ( .A ( aps_rename_508_ ) , + .Y ( BUF_net_95 ) ) ; endmodule @@ -40617,10 +40585,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_507_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_91 ( .A ( BUF_net_93 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) , - .Y ( BUF_net_93 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_90 ( .A ( BUF_net_92 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_91 ( .A ( BUF_net_92 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_92 ( .A ( aps_rename_507_ ) , + .Y ( BUF_net_92 ) ) ; endmodule @@ -40724,8 +40692,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_2 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb4 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -40739,7 +40706,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_1 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -40967,20 +40934,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_6 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_7 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_mem_6 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41021,7 +40988,6 @@ input p1 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -41034,12 +41000,10 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , .p1 ( p1 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_2 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( @@ -41058,21 +41022,21 @@ grid_clb_mux_tree_size2_8 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_9 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_10 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , .out ( mux_tree_size2_2_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( .in ( { @@ -41080,7 +41044,7 @@ grid_clb_mux_tree_size2_11 mux_ff_1_D_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_8 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41130,14 +41094,12 @@ input p1 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_1 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p0 ( p0 ) , .p1 ( p1 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; endmodule @@ -41205,34 +41167,34 @@ sky130_fd_sc_hd__buf_1 FTB_4__3 ( .A ( mem_out[1] ) , .X ( ccff_tail[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_5 ( in , sram , sram_inv , out , p0 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p0 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p0 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule -module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_4 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -41252,10 +41214,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_506_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_88 ( .A ( BUF_net_90 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_89 ( .A ( BUF_net_90 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_90 ( .A ( aps_rename_506_ ) , - .Y ( BUF_net_90 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_87 ( .A ( BUF_net_89 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) , + .Y ( BUF_net_89 ) ) ; endmodule @@ -41274,10 +41236,10 @@ sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( aps_rename_505_ ) ) ; -sky130_fd_sc_hd__inv_2 BINV_R_85 ( .A ( BUF_net_87 ) , .Y ( out[0] ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_86 ( .A ( BUF_net_87 ) , .Y ( p_abuf0 ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_87 ( .A ( aps_rename_505_ ) , - .Y ( BUF_net_87 ) ) ; +sky130_fd_sc_hd__inv_2 BINV_R_84 ( .A ( BUF_net_86 ) , .Y ( out[0] ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_85 ( .A ( BUF_net_86 ) , .Y ( p_abuf0 ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_86 ( .A ( aps_rename_505_ ) , + .Y ( BUF_net_86 ) ) ; endmodule @@ -41359,18 +41321,18 @@ sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , endmodule -module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p1 ) ; +module grid_clb_mux_tree_size2_0 ( in , sram , sram_inv , out , p4 ) ; input [0:1] in ; input [0:1] sram ; input [0:1] sram_inv ; output [0:0] out ; -input p1 ; +input p4 ; wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ; sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) , .S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ; -sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p1 ) , +sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ ( .A0 ( p4 ) , .A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) , .X ( out[0] ) ) ; endmodule @@ -41381,8 +41343,7 @@ input A1 ; input S ; output X ; -sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , - .X ( X_gOb1 ) ) ; +sky130_fd_sc_hd__mux2_1 MUX2 ( .A0 ( A0 ) , .A1 ( A1 ) , .S ( S ) , .X ( X ) ) ; endmodule @@ -41396,7 +41357,7 @@ output [0:0] carry_follower_cout ; grid_clb_sky130_fd_sc_hd__mux2_1_wrapper_0 sky130_fd_sc_hd__mux2_1_wrapper_0_ ( .A0 ( carry_follower_a[0] ) , .A1 ( carry_follower_b[0] ) , - .S ( carry_follower_cin[0] ) , .X ( SYNOPSYS_UNCONNECTED_1 ) ) ; + .S ( carry_follower_cin[0] ) , .X ( carry_follower_cout[0] ) ) ; endmodule @@ -41408,7 +41369,7 @@ input [0:0] ccff_head ; output [0:0] ccff_tail ; output [0:16] mem_out ; -sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_201 ) , +sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ropt_net_203 ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ; sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ; @@ -41443,20 +41404,20 @@ sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_15_ ( .D ( mem_out[14] ) , sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_16_ ( .D ( mem_out[15] ) , .CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[16] ) ) ; sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[16] ) , .X ( ccff_tail[0] ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1630 ( .A ( ccff_head[0] ) , - .X ( copt_net_189 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( copt_net_194 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1631 ( .A ( ccff_head[0] ) , .X ( copt_net_190 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_190 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1632 ( .A ( copt_net_195 ) , .X ( copt_net_191 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_189 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1633 ( .A ( copt_net_191 ) , .X ( copt_net_192 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_192 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1634 ( .A ( copt_net_190 ) , .X ( copt_net_193 ) ) ; -sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_193 ) , +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1635 ( .A ( copt_net_192 ) , .X ( copt_net_194 ) ) ; -sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1642 ( .A ( copt_net_191 ) , - .X ( ropt_net_201 ) ) ; +sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1636 ( .A ( copt_net_193 ) , + .X ( copt_net_195 ) ) ; +sky130_fd_sc_hd__dlygate4sd1_1 ropt_h_inst_1644 ( .A ( copt_net_194 ) , + .X ( ropt_net_203 ) ) ; endmodule @@ -41602,7 +41563,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( pReset , prog_clk , frac_logic_in , frac_logic_cin , ccff_head , - frac_logic_out , frac_logic_cout , ccff_tail , p1 , p4 ) ; + frac_logic_out , frac_logic_cout , ccff_tail , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:3] frac_logic_in ; @@ -41611,7 +41572,6 @@ input [0:0] ccff_head ; output [0:1] frac_logic_out ; output [0:0] frac_logic_cout ; output [0:0] ccff_tail ; -input p1 ; input p4 ; wire [0:0] direct_interc_5_out ; @@ -41639,20 +41599,20 @@ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__carry_follower_0 ( .carry_follower_a ( direct_interc_5_out ) , .carry_follower_b ( frac_logic_cin ) , - .carry_follower_cin ( direct_interc_7_out ) , - .carry_follower_cout ( { SYNOPSYS_UNCONNECTED_1 } ) ) ; + .carry_follower_cin ( direct_interc_7_out ) , + .carry_follower_cout ( frac_logic_cout ) ) ; grid_clb_mux_tree_size2_0 mux_frac_logic_out_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut4_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_mode_default__frac_lut4_0_frac_lut4_lut3_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , - .out ( frac_logic_out[0] ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , + .out ( frac_logic_out[0] ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_1 mux_frac_lut4_0_in_2 ( .in ( { frac_logic_cin[0] , frac_logic_in[2] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( mux_tree_size2_1_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_mem_0 mem_frac_logic_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , @@ -41669,7 +41629,7 @@ module grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( pReset , prog_clk , Test_en , fabric_in , fabric_reg_in , fabric_sc_in , fabric_cin , fabric_reset , fabric_clk , ccff_head , fabric_out , fabric_reg_out , fabric_sc_out , fabric_cout , ccff_tail , p_abuf0 , - p_abuf1 , p1 , p4 ) ; + p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -41687,13 +41647,13 @@ output [0:0] fabric_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q ; wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ; wire [0:1] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ; -wire [0:0] logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ; wire [0:1] mux_tree_size2_0_sram ; wire [0:1] mux_tree_size2_1_sram ; wire [0:0] mux_tree_size2_2_out ; @@ -41706,14 +41666,12 @@ wire [0:0] mux_tree_size2_mem_2_ccff_tail ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , - .frac_logic_in ( fabric_in ) , - .frac_logic_cin ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_undriven_frac_logic_cin ) , + .frac_logic_in ( fabric_in ) , .frac_logic_cin ( fabric_cin ) , .ccff_head ( ccff_head ) , - .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , - .frac_logic_cout ( { SYNOPSYS_UNCONNECTED_1 } ) , - + .frac_logic_out ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out ) , + .frac_logic_cout ( fabric_cout ) , .ccff_tail ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , - .p1 ( p1 ) , .p4 ( p4 ) ) ; + .p4 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0 ( .Test_en ( Test_en ) , .ff_D ( mux_tree_size2_2_out ) , .ff_DI ( fabric_sc_in ) , .ff_reset ( fabric_reset ) , @@ -41730,30 +41688,30 @@ grid_clb_mux_tree_size2_2 mux_fabric_out_0 ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] } ) , .sram ( mux_tree_size2_0_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_2 , SYNOPSYS_UNCONNECTED_3 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) , .out ( fabric_out[0] ) , .p_abuf0 ( p_abuf0 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_3 mux_fabric_out_1 ( .in ( { fabric_sc_out[0] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] } ) , .sram ( mux_tree_size2_1_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 } ) , + .sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) , .out ( fabric_out[1] ) , .p_abuf0 ( p_abuf1 ) , .p1 ( p1 ) ) ; grid_clb_mux_tree_size2_4 mux_ff_0_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[0] , fabric_reg_in[0] } ) , .sram ( mux_tree_size2_2_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_6 , SYNOPSYS_UNCONNECTED_7 } ) , - .out ( mux_tree_size2_2_out ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) , + .out ( mux_tree_size2_2_out ) , .p4 ( p4 ) ) ; grid_clb_mux_tree_size2_5 mux_ff_1_D_0 ( .in ( { logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_frac_logic_out[1] , logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0_ff_Q[0] } ) , .sram ( mux_tree_size2_3_sram ) , - .sram_inv ( { SYNOPSYS_UNCONNECTED_8 , SYNOPSYS_UNCONNECTED_9 } ) , - .out ( mux_tree_size2_3_out ) , .p1 ( p1 ) ) ; + .sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) , + .out ( mux_tree_size2_3_out ) , .p0 ( p0 ) ) ; grid_clb_mux_tree_size2_mem_2 mem_fabric_out_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__frac_logic_0_ccff_tail ) , @@ -41778,7 +41736,7 @@ endmodule module grid_clb_logical_tile_clb_mode_default__fle_0 ( pReset , prog_clk , Test_en , fle_in , fle_reg_in , fle_sc_in , fle_cin , fle_reset , fle_clk , ccff_head , fle_out , fle_reg_out , fle_sc_out , fle_cout , - ccff_tail , p_abuf0 , p_abuf1 , p1 , p4 ) ; + ccff_tail , p_abuf0 , p_abuf1 , p0 , p1 , p4 ) ; input [0:0] pReset ; input [0:0] prog_clk ; input [0:0] Test_en ; @@ -41796,20 +41754,20 @@ output [0:0] fle_cout ; output [0:0] ccff_tail ; output p_abuf0 ; output p_abuf1 ; +input p0 ; input p1 ; input p4 ; grid_clb_logical_tile_clb_mode_default__fle_mode_physical__fabric_0 logical_tile_clb_mode_default__fle_mode_physical__fabric_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fabric_in ( fle_in ) , .fabric_reg_in ( fle_reg_in ) , - .fabric_sc_in ( fle_sc_in ) , - .fabric_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , + .fabric_sc_in ( fle_sc_in ) , .fabric_cin ( fle_cin ) , .fabric_reset ( fle_reset ) , .fabric_clk ( fle_clk ) , .ccff_head ( ccff_head ) , .fabric_out ( fle_out ) , - .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , - .fabric_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , - .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , - .p1 ( p1 ) , .p4 ( p4 ) ) ; + .fabric_reg_out ( fle_reg_out ) , .fabric_sc_out ( fle_sc_out ) , + .fabric_cout ( fle_cout ) , .ccff_tail ( ccff_tail ) , + .p_abuf0 ( p_abuf0 ) , .p_abuf1 ( p_abuf1 ) , .p0 ( p0 ) , .p1 ( p1 ) , + .p4 ( p4 ) ) ; endmodule @@ -41876,12 +41834,19 @@ input p4 ; input p5 ; wire [0:0] direct_interc_32_out ; +wire [0:0] direct_interc_34_out ; wire [0:0] direct_interc_41_out ; +wire [0:0] direct_interc_43_out ; wire [0:0] direct_interc_50_out ; +wire [0:0] direct_interc_52_out ; wire [0:0] direct_interc_59_out ; +wire [0:0] direct_interc_61_out ; wire [0:0] direct_interc_68_out ; +wire [0:0] direct_interc_70_out ; wire [0:0] direct_interc_77_out ; +wire [0:0] direct_interc_79_out ; wire [0:0] direct_interc_86_out ; +wire [0:0] direct_interc_88_out ; wire [0:0] logical_tile_clb_mode_default__fle_0_ccff_tail ; wire [0:0] logical_tile_clb_mode_default__fle_0_fle_sc_out ; wire [0:0] logical_tile_clb_mode_default__fle_1_ccff_tail ; @@ -41900,42 +41865,42 @@ wire [0:0] logical_tile_clb_mode_default__fle_6_fle_sc_out ; grid_clb_logical_tile_clb_mode_default__fle_0 logical_tile_clb_mode_default__fle_0 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I0[0] , clb_I0[1] , clb_I0i[0] , clb_I0i[1] } ) , - .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_reg_in ( clb_reg_in ) , .fle_sc_in ( clb_sc_in ) , + .fle_cin ( clb_cin ) , .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , .ccff_head ( ccff_head ) , .fle_out ( { clb_O[1] , clb_O[0] } ) , .fle_reg_out ( direct_interc_32_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_2 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cout ( direct_interc_34_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , - .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p1 ( p2 ) , .p4 ( p5 ) ) ; + .p_abuf0 ( p_abuf1 ) , .p_abuf1 ( p_abuf2 ) , .p0 ( p0 ) , .p1 ( p2 ) , + .p4 ( p5 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_1 logical_tile_clb_mode_default__fle_1 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I1[0] , clb_I1[1] , clb_I1i[0] , clb_I1i[1] } ) , .fle_reg_in ( direct_interc_32_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_3 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_0_fle_sc_out ) , + .fle_cin ( direct_interc_34_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_0_ccff_tail ) , .fle_out ( { clb_O[3] , clb_O[2] } ) , .fle_reg_out ( direct_interc_41_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_4 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cout ( direct_interc_43_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .p_abuf0 ( p_abuf3 ) , .p_abuf1 ( p_abuf4 ) , .p0 ( p0 ) , .p1 ( p2 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_2 logical_tile_clb_mode_default__fle_2 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I2[0] , clb_I2[1] , clb_I2i[0] , clb_I2i[1] } ) , .fle_reg_in ( direct_interc_41_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_5 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_1_fle_sc_out ) , + .fle_cin ( direct_interc_43_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_1_ccff_tail ) , .fle_out ( { clb_O[5] , clb_O[4] } ) , .fle_reg_out ( direct_interc_50_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_6 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cout ( direct_interc_52_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .p_abuf0 ( p_abuf5 ) , .p_abuf1 ( p_abuf6 ) , .p0 ( p0 ) , .p2 ( p3 ) , .p4 ( p5 ) ) ; @@ -41943,71 +41908,71 @@ grid_clb_logical_tile_clb_mode_default__fle_3 logical_tile_clb_mode_default__fle .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I3[0] , clb_I3[1] , clb_I3i[0] , clb_I3i[1] } ) , .fle_reg_in ( direct_interc_50_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_7 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_2_fle_sc_out ) , + .fle_cin ( direct_interc_52_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_2_ccff_tail ) , .fle_out ( { clb_O[7] , clb_O[6] } ) , .fle_reg_out ( direct_interc_59_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_8 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cout ( direct_interc_61_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .p_abuf0 ( p_abuf7 ) , .p_abuf1 ( p_abuf8 ) , .p2 ( p3 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_4 logical_tile_clb_mode_default__fle_4 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I4[0] , clb_I4[1] , clb_I4i[0] , clb_I4i[1] } ) , .fle_reg_in ( direct_interc_59_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_9 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_3_fle_sc_out ) , + .fle_cin ( direct_interc_61_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_3_ccff_tail ) , .fle_out ( { clb_O[9] , clb_O[8] } ) , .fle_reg_out ( direct_interc_68_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_10 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cout ( direct_interc_70_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , - .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p2 ( p3 ) , .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf9 ) , .p_abuf1 ( p_abuf10 ) , .p0 ( p0 ) , .p2 ( p3 ) , + .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_5 logical_tile_clb_mode_default__fle_5 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I5[0] , clb_I5[1] , clb_I5i[0] , clb_I5i[1] } ) , .fle_reg_in ( direct_interc_68_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_11 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_4_fle_sc_out ) , + .fle_cin ( direct_interc_70_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_4_ccff_tail ) , .fle_out ( { clb_O[11] , clb_O[10] } ) , .fle_reg_out ( direct_interc_77_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_12 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cout ( direct_interc_79_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .p_abuf0 ( p_abuf11 ) , .p_abuf1 ( p_abuf12 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle_6 logical_tile_clb_mode_default__fle_6 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I6[0] , clb_I6[1] , clb_I6i[0] , clb_I6i[1] } ) , .fle_reg_in ( direct_interc_77_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_13 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_5_fle_sc_out ) , + .fle_cin ( direct_interc_79_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_5_ccff_tail ) , .fle_out ( { clb_O[13] , clb_O[12] } ) , .fle_reg_out ( direct_interc_86_out ) , - .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cout ( { SYNOPSYS_UNCONNECTED_14 } ) , + .fle_sc_out ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cout ( direct_interc_88_out ) , .ccff_tail ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , - .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p0 ) , .p1 ( p1 ) , - .p3 ( p4 ) ) ; + .p_abuf0 ( p_abuf13 ) , .p_abuf1 ( p_abuf14 ) , .p0 ( p1 ) , .p3 ( p4 ) ) ; grid_clb_logical_tile_clb_mode_default__fle logical_tile_clb_mode_default__fle_7 ( .pReset ( pReset ) , .prog_clk ( prog_clk ) , .Test_en ( Test_en ) , .fle_in ( { clb_I7[0] , clb_I7[1] , clb_I7i[0] , clb_I7i[1] } ) , .fle_reg_in ( direct_interc_86_out ) , - .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , - .fle_cin ( { SYNOPSYS_UNCONNECTED_15 } ) , - .fle_reset ( clb_reset ) , .fle_clk ( clb_clk ) , + .fle_sc_in ( logical_tile_clb_mode_default__fle_6_fle_sc_out ) , + .fle_cin ( direct_interc_88_out ) , .fle_reset ( clb_reset ) , + .fle_clk ( clb_clk ) , .ccff_head ( logical_tile_clb_mode_default__fle_6_ccff_tail ) , .fle_out ( { clb_O[15] , clb_O[14] } ) , .fle_reg_out ( clb_reg_out ) , .fle_sc_out ( clb_sc_out ) , .fle_cout ( clb_cout ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( p_abuf0 ) , - .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p0 ) , .p1 ( p1 ) ) ; + .p_abuf1 ( p_abuf15 ) , .p_abuf2 ( p_abuf16 ) , .p0 ( p1 ) ) ; endmodule @@ -42211,17 +42176,17 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( right_width_0_height_0__pin_31_[0] } ) , .clb_reg_in ( top_width_0_height_0__pin_32_ ) , .clb_sc_in ( { SC_IN_BOT } ) , - .clb_cin ( { SYNOPSYS_UNCONNECTED_1 } ) , - .clb_reset ( Reset ) , .clb_clk ( clk ) , .ccff_head ( ccff_head ) , - .clb_O ( { aps_rename_522_ , aps_rename_523_ , aps_rename_524_ , - aps_rename_525_ , aps_rename_526_ , aps_rename_527_ , - aps_rename_528_ , aps_rename_529_ , aps_rename_530_ , - aps_rename_531_ , right_width_0_height_0__pin_46_lower[0] , - right_width_0_height_0__pin_47_lower[0] , aps_rename_534_ , - aps_rename_535_ , right_width_0_height_0__pin_50_lower[0] , - aps_rename_537_ } ) , + .clb_cin ( top_width_0_height_0__pin_34_ ) , .clb_reset ( Reset ) , + .clb_clk ( clk ) , .ccff_head ( ccff_head ) , + .clb_O ( { aps_rename_523_ , aps_rename_524_ , aps_rename_525_ , + aps_rename_526_ , aps_rename_527_ , aps_rename_528_ , + aps_rename_529_ , aps_rename_530_ , aps_rename_531_ , + aps_rename_532_ , right_width_0_height_0__pin_46_lower[0] , + right_width_0_height_0__pin_47_lower[0] , aps_rename_535_ , + aps_rename_536_ , right_width_0_height_0__pin_50_lower[0] , + aps_rename_538_ } ) , .clb_reg_out ( bottom_width_0_height_0__pin_52_ ) , - .clb_sc_out ( { aps_rename_538_ } ) , + .clb_sc_out ( { aps_rename_539_ } ) , .clb_cout ( bottom_width_0_height_0__pin_54_ ) , .ccff_tail ( ccff_tail ) , .p_abuf0 ( SC_OUT_BOT ) , .p_abuf1 ( top_width_0_height_0__pin_37_lower[0] ) , @@ -42238,98 +42203,98 @@ grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .p_abuf13 ( right_width_0_height_0__pin_49_lower[0] ) , .p_abuf14 ( right_width_0_height_0__pin_48_lower[0] ) , .p_abuf15 ( right_width_0_height_0__pin_51_lower[0] ) , - .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_179 ) , .p1 ( optlc_net_180 ) , - .p2 ( optlc_net_181 ) , .p3 ( optlc_net_182 ) , .p4 ( optlc_net_183 ) , - .p5 ( optlc_net_184 ) ) ; + .p_abuf16 ( p_abuf16 ) , .p0 ( optlc_net_180 ) , .p1 ( optlc_net_181 ) , + .p2 ( optlc_net_182 ) , .p3 ( optlc_net_183 ) , .p4 ( optlc_net_184 ) , + .p5 ( optlc_net_185 ) ) ; sky130_fd_sc_hd__buf_2 Test_en_FTB00 ( .A ( Test_en_W_in ) , .X ( Test_en[0] ) ) ; sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_W_in ) , - .X ( aps_rename_539_ ) ) ; -sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , .X ( aps_rename_540_ ) ) ; +sky130_fd_sc_hd__buf_1 Test_en_E_FTB01 ( .A ( Test_en_W_in ) , + .X ( aps_rename_541_ ) ) ; sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ; sky130_fd_sc_hd__buf_4 Reset_FTB00 ( .A ( Reset_W_in ) , .X ( Reset[0] ) ) ; sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_W_in ) , - .X ( aps_rename_541_ ) ) ; -sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , .X ( aps_rename_542_ ) ) ; +sky130_fd_sc_hd__buf_1 Reset_E_FTB01 ( .A ( Reset_W_in ) , + .X ( aps_rename_543_ ) ) ; sky130_fd_sc_hd__buf_6 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) , .X ( prog_clk_0 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_1185 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_2186 ) ) ; -sky130_fd_sc_hd__buf_4 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_3187 ) ) ; + .X ( ctsbuf_net_1186 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_E_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_2187 ) ) ; +sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) , + .X ( ctsbuf_net_3188 ) ) ; sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_S_in ) , - .X ( ctsbuf_net_4188 ) ) ; + .X ( ctsbuf_net_4189 ) ) ; sky130_fd_sc_hd__buf_1 clk_0_FTB00 ( .A ( clk_0_S_in ) , .X ( clk[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_522_ ) , +sky130_fd_sc_hd__buf_6 FTB_65__64 ( .A ( aps_rename_523_ ) , .X ( top_width_0_height_0__pin_36_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_523_ ) , +sky130_fd_sc_hd__buf_6 FTB_66__65 ( .A ( aps_rename_524_ ) , .X ( top_width_0_height_0__pin_37_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_524_ ) , +sky130_fd_sc_hd__buf_6 FTB_67__66 ( .A ( aps_rename_525_ ) , .X ( top_width_0_height_0__pin_38_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_525_ ) , +sky130_fd_sc_hd__buf_6 FTB_68__67 ( .A ( aps_rename_526_ ) , .X ( top_width_0_height_0__pin_39_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_526_ ) , +sky130_fd_sc_hd__buf_6 FTB_69__68 ( .A ( aps_rename_527_ ) , .X ( top_width_0_height_0__pin_40_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_527_ ) , +sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( aps_rename_528_ ) , .X ( top_width_0_height_0__pin_41_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_528_ ) , +sky130_fd_sc_hd__buf_6 FTB_71__70 ( .A ( aps_rename_529_ ) , .X ( top_width_0_height_0__pin_42_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_529_ ) , +sky130_fd_sc_hd__buf_6 FTB_72__71 ( .A ( aps_rename_530_ ) , .X ( top_width_0_height_0__pin_43_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_530_ ) , +sky130_fd_sc_hd__buf_6 FTB_73__72 ( .A ( aps_rename_531_ ) , .X ( right_width_0_height_0__pin_44_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_531_ ) , +sky130_fd_sc_hd__buf_6 FTB_74__73 ( .A ( aps_rename_532_ ) , .X ( right_width_0_height_0__pin_45_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_75__74 ( .A ( p_abuf12 ) , .X ( right_width_0_height_0__pin_46_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_76__75 ( .A ( p_abuf11 ) , .X ( right_width_0_height_0__pin_47_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_534_ ) , +sky130_fd_sc_hd__buf_6 FTB_77__76 ( .A ( aps_rename_535_ ) , .X ( right_width_0_height_0__pin_48_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_535_ ) , +sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( aps_rename_536_ ) , .X ( right_width_0_height_0__pin_49_upper[0] ) ) ; sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( p_abuf16 ) , .X ( right_width_0_height_0__pin_50_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_537_ ) , +sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( aps_rename_538_ ) , .X ( right_width_0_height_0__pin_51_upper[0] ) ) ; -sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_538_ ) , +sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( aps_rename_539_ ) , .X ( SC_OUT_TOP ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_133 ( .A ( BUF_net_134 ) , +sky130_fd_sc_hd__inv_8 BINV_R_134 ( .A ( BUF_net_135 ) , .Y ( Test_en_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_134 ( .A ( aps_rename_539_ ) , - .Y ( BUF_net_134 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_135 ( .A ( BUF_net_136 ) , +sky130_fd_sc_hd__inv_1 BINV_R_135 ( .A ( aps_rename_540_ ) , + .Y ( BUF_net_135 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_136 ( .A ( BUF_net_137 ) , .Y ( Test_en_E_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_136 ( .A ( aps_rename_540_ ) , - .Y ( BUF_net_136 ) ) ; -sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) , .Y ( Reset_W_out ) ) ; -sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( aps_rename_541_ ) , - .Y ( BUF_net_138 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_141 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , - .HI ( optlc_net_179 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_143 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , +sky130_fd_sc_hd__inv_1 BINV_R_137 ( .A ( aps_rename_541_ ) , + .Y ( BUF_net_137 ) ) ; +sky130_fd_sc_hd__inv_8 BINV_R_138 ( .A ( BUF_net_139 ) , .Y ( Reset_W_out ) ) ; +sky130_fd_sc_hd__inv_1 BINV_R_139 ( .A ( aps_rename_542_ ) , + .Y ( BUF_net_139 ) ) ; +sky130_fd_sc_hd__conb_1 optlc_142 ( .LO ( SYNOPSYS_UNCONNECTED_1 ) , .HI ( optlc_net_180 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_145 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , +sky130_fd_sc_hd__conb_1 optlc_144 ( .LO ( SYNOPSYS_UNCONNECTED_2 ) , .HI ( optlc_net_181 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_147 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , +sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_3 ) , .HI ( optlc_net_182 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_149 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , +sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_4 ) , .HI ( optlc_net_183 ) ) ; -sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_7 ) , +sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) , .HI ( optlc_net_184 ) ) ; -sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_152 ( .A ( aps_rename_542_ ) , +sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_6 ) , + .HI ( optlc_net_185 ) ) ; +sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_153 ( .A ( aps_rename_543_ ) , .X ( Reset_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_3981325 ( .A ( ctsbuf_net_1185 ) , +sky130_fd_sc_hd__buf_6 cts_buf_3981326 ( .A ( ctsbuf_net_1186 ) , .X ( prog_clk_0_S_out ) ) ; -sky130_fd_sc_hd__bufbuf_16 cts_buf_4031330 ( .A ( ctsbuf_net_2186 ) , +sky130_fd_sc_hd__bufbuf_16 cts_buf_4031331 ( .A ( ctsbuf_net_2187 ) , .X ( prog_clk_0_E_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4081335 ( .A ( ctsbuf_net_3187 ) , +sky130_fd_sc_hd__clkbuf_8 cts_buf_4081336 ( .A ( ctsbuf_net_3188 ) , .X ( prog_clk_0_W_out ) ) ; -sky130_fd_sc_hd__buf_6 cts_buf_4131340 ( .A ( ctsbuf_net_4188 ) , +sky130_fd_sc_hd__buf_6 cts_buf_4131341 ( .A ( ctsbuf_net_4189 ) , .X ( prog_clk_0_N_out ) ) ; endmodule diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv index 4ba7f3e..4213bfc 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/module_utilization.tsv @@ -15,4 +15,4 @@ |fpga_core_uut/cby_0__12_ | 23.46 | 6406.144000 | 5120 | 12 | 815 |fpga_core_uut/cby_11__12_ | 82.05 | 6406.144000 | 5120 | 132 | 444 |fpga_core_uut/cby_12__12_ | 82.64 | 6406.144000 | 5120 | 12 | 486 -|fpga_core_uut/grid_clb_12__12_ | 68.26 | 14814.208000 | 11840 | 144 | 1370 +|fpga_core_uut/grid_clb_12__12_ | 68.3 | 14814.208000 | 11840 | 144 | 1083 diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv index 6ed6224..1c80624 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/std_cell_utilization.tsv @@ -1,31 +1,31 @@ Ref Name Total Area Utilization_% Instance Count ---------------------------------------------------------------------------------------------------- sky130_fd_sc_hd__dfrtp_1 1971015.360000 19.18 78765 - sky130_fd_sc_hd__mux2_1 1591488.864000 15.49 141330 + sky130_fd_sc_hd__mux2_1 1602839.750400 15.60 142338 sky130_fd_sc_hd__buf_8 452744.217600 4.41 30154 - sky130_fd_sc_hd__buf_6 150252.854400 1.46 13343 + sky130_fd_sc_hd__buf_6 148631.299200 1.45 13199 sky130_fd_sc_hd__buf_1 88960.320000 0.87 23700 - sky130_fd_sc_hd__inv_8 76584.700800 0.75 6801 + sky130_fd_sc_hd__inv_8 78206.256000 0.76 6945 sky130_fd_sc_hd__sdfrtp_1 72069.120000 0.70 2304 sky130_fd_sc_hd__dlygate4sd3_1 56293.990400 0.55 5624 - sky130_fd_sc_hd__mux2_2 44311.248000 0.43 3935 sky130_fd_sc_hd__inv_1 42156.681600 0.41 11231 - sky130_fd_sc_hd__buf_4 39112.512000 0.38 5210 + sky130_fd_sc_hd__buf_4 36950.438400 0.36 4922 sky130_fd_sc_hd__bufbuf_16 36239.756800 0.35 1114 + sky130_fd_sc_hd__mux2_2 32960.361600 0.32 2927 sky130_fd_sc_hd__conb_1 25592.044800 0.25 6818 sky130_fd_sc_hd__inv_2 13696.886400 0.13 3649 sky130_fd_sc_hd__or2_0 7206.912000 0.07 1152 sky130_fd_sc_hd__inv_6 6235.980800 0.06 712 sky130_fd_sc_hd__ebufn_4 5758.022400 0.06 354 - sky130_fd_sc_hd__clkbuf_1 2747.635200 0.03 732 + sky130_fd_sc_hd__clkbuf_1 3828.672000 0.04 1020 sky130_fd_sc_hd__dlygate4sd2_1 2417.318400 0.02 276 + sky130_fd_sc_hd__clkbuf_8 2147.059200 0.02 156 sky130_fd_sc_hd__buf_2 1436.377600 0.01 287 sky130_fd_sc_hd__dlygate4sd1_1 1366.310400 0.01 156 sky130_fd_sc_hd__nand2b_1 825.792000 0.01 132 sky130_fd_sc_hd__buf_16 633.107200 0.01 23 sky130_fd_sc_hd__inv_4 450.432000 0.00 72 sky130_fd_sc_hd__buf_12 220.211200 0.00 11 - sky130_fd_sc_hd__clkbuf_8 165.158400 0.00 12 sky130_fd_sc_hd__or2b_4 135.129600 0.00 12 FPGA_BBOX_AREA 6714279.5264 CORE_BBOX_AREA 10276128.1216 diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt index 5f575fc..197469e 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/rpts_icc2/timing_reports.txt @@ -6,7 +6,7 @@ Report : clock timing -setup Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 14 01:56:02 2020 +Date : Mon Dec 21 23:13:06 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -16,7 +16,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.143 11.143 rp-+ nominal + fpga_core_uut/sb_11__11_/mem_right_track_2/sky130_fd_sc_hd__dfrtp_1_3_/CLK 6.164 0.000 -- 11.140 11.140 rp-+ nominal --------------------------------------------------------------------------------------------------- Mode: full_chip @@ -25,7 +25,7 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) --- Latency --- Clock Pin Trans Source Offset Network Total Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.710 0.000 -- 6.927 6.927 rp-+ nominal + fpga_core_uut/grid_clb_11__12_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 0.701 0.000 -- 6.921 6.921 rp-+ nominal --------------------------------------------------------------------------------------------------- **************************************** Report : clock timing @@ -34,7 +34,7 @@ Report : clock timing -setup Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 14 01:56:02 2020 +Date : Mon Dec 21 23:13:07 2020 **************************************** Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -43,8 +43,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) Clock Pin Latency Skew Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/sb_10__8_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 9.828 rp-+ nominal - fpga_core_uut/cbx_10__8_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 5.994 3.835 rp-+ nominal + fpga_core_uut/sb_1__5_/mem_left_track_53/sky130_fd_sc_hd__dfrtp_1_2_/CLK 10.371 rp-+ nominal + fpga_core_uut/cbx_1__5_/mem_top_ipin_0/sky130_fd_sc_hd__dfrtp_1_0_/CLK 6.542 3.829 rp-+ nominal --------------------------------------------------------------------------------------------------- @@ -53,8 +53,8 @@ Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) Clock Pin Latency Skew Corner --------------------------------------------------------------------------------------------------- - fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.115 rp-+ nominal - fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.386 0.729 rp-+ nominal + fpga_core_uut/grid_clb_6__2_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_7/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_1/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 6.109 rp-+ nominal + fpga_core_uut/grid_clb_6__3_/logical_tile_clb_mode_clb__0/logical_tile_clb_mode_default__fle_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_0/logical_tile_clb_mode_default__fle_mode_physical__fabric_mode_default__ff_0/sky130_fd_sc_hd__sdfrtp_1_0_/CLK 5.381 0.729 rp-+ nominal --------------------------------------------------------------------------------------------------- Information: Timer using 'PrimeTime Delay Calculation, AWP'. (TIM-050) @@ -63,7 +63,7 @@ Report : global timing -format { narrow } Design : fpga_top Version: P-2019.03-SP4 -Date : Mon Dec 14 01:56:04 2020 +Date : Mon Dec 21 23:13:09 2020 **************************************** No setup violations found. diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef.gz b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef.gz index 73920fb..7d5865c 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef.gz and b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef.gz differ diff --git a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef.gz b/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef.gz index 772358b..b9a4807 100644 Binary files a/FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__1__icv_in_design.nominal_25.spef.gz and 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