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Enabling custom yosys script only for and gate design, will enable later for other designs when yosys submodule is updated

This commit is contained in:
Lalit Sharma 2021-01-07 01:15:41 -08:00
parent 847d0ec8f6
commit 4128f4cd1b
1 changed files with 0 additions and 2 deletions
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SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf
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@ -60,9 +60,7 @@ bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.
bench1_top = and2_latch
bench1_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench2_top = bin2bcd
bench2_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench3_top = counter
bench3_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
bench4_top = routing_test
# RS decoder needs 1.5k LUT4, exceeding device capacity
bench5_top = rs_decoder_top