[CI] Precheck related updates

.github/deploy_sofa.yaml

@@ -19,6 +19,8 @@ env:
     lnis-uofu/Caravel-SOFA-HD
   REPO_KEY: &REPO_KEY
     ${{ secrets.SOFA_HD_KEY }}
+  CARAVEL_COMPARE_COMMIT: &CARAVEL_COMPARE_COMMIT
+    f48448d4736bd6d56fed4dbf7f9cc50552d8745d
 
 on:
   push:
@@ -68,27 +70,14 @@ jobs:
         run: cd /usr/local/workspace && pwd && ls && bash ./SOFA-Chips/.github/workflows/perform_precheck.sh
 
     - name: Deploy files
-      # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
       run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
 
-    - name: Deploy Changes
-      uses: peaceiris/actions-gh-pages@v3
-      # if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
-      with:
-        user_name: "lnis.uofu"
-        user_email: "lnis.uofu@gmail.com"
-        deploy_key: *REPO_KEY
-        external_repository: *DEST_REPO
-        publish_dir: *DEST_DIR
-        publish_branch: master
-        disable_nojekyll: true
-        commit_message: '[Deployment] ${{ github.event.head_commit.message }}'
+    - name: Local log
+      if: ${{ github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged' }}
+      run:
+        git status
 
-    # - name: Deploy files to localbranch
-    #   if: ${{! (github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged') }}
-    #   run: bash ./SOFA-Chips/.github/workflows/sync_repo.sh
-
-    # - name: Deploy Changes localbranch
+    #  - name: Deploy Changes localbranch
     #   uses: peaceiris/actions-gh-pages@v3
     #   if: ${{! (github.event_name == 'pull_request' && contains(github.ref, "master") && github.event.action == 'merged') }}
     #   with:

.github/workflows/perform_precheck.sh

@@ -36,8 +36,6 @@ echo "[Info] Finished shiping chip with Klayout"
 rm -rf ./gds/fpga_top*
 rm -rf ./gds/user_project_wrapper_empty.gds
 rm -rf ./gds/user_proj_example.gds
-rm -rf .travis*
-rm -f .travis.yml
 mv ./gds/caravel_merged.gds ./gds/caravel.gds
 
 # = = = = = = = = =  Build Caravel with Magic = = = = = = = = = = = = = = = = =
@@ -74,4 +72,11 @@ rm -rf user_project_wrapper.mag
 rm -rf gds/caravel.mag
 rm -rf magic_drc.log
 git checkout HEAD -- ./mag/user_project_wrapper.mag
-git checkout HEAD -- ./mag/user_project_wrapper.mag
+git checkout HEAD -- ./mag/user_project_wrapper.mag
+
+echo ${CARAVEL_COMPARE_COMMIT}
+if [[ 0 -eq $(git cat-file -e $CARAVEL_COMPARE_COMMIT) ]]; then
+    git diff --stat $CARAVEL_COMPARE_COMMIT . > \
+    /usr/local/workspace/${DEST_DIR}/checks/compare_caravel.txt
+    echo "[Info] Create compare_caravel.txt"
+fi

.github/workflows/sync_repo.sh

@@ -16,11 +16,14 @@ done
 
 cd ${DEST_DIR}
 
-[ -s source_commit_hash.txt ] || echo "----------" > source_commit_hash.txt
-sed -i -e "s/^/\n/" source_commit_hash.txt
-sed -i -e "s/^/${GITHUB_SHA}\n/" source_commit_hash.txt
-sed -i -e "s/^/$(date)\n/" source_commit_hash.txt
+[ -s source_commit_hash.txt ] || echo "---- Start ----" > source_commit_hash.txt
 
+sed -i "1i  GITHUB_SHA ${GITHUB_SHA:--}" source_commit_hash.txt
+sed -i "1i  Date       $(date)" source_commit_hash.txt
+sed -i '1i  = = = = = = = = = = = = = = = =' source_commit_hash.txt
 
 # Clean up file from repo
-git checkout master qflow
+git checkout master qflow
+rm -rf .travis*
+rm -f .travis.yml
+find . -xtype l -delete

HDL/common/user_project_wrapper_integration.v

@@ -0,0 +1,116 @@
+module user_project_wrapper(
+// Power pins
+    vccd1, vssd1, vccd2, vssd2,
+    vdda1, vssa1, vdda2, vssa2,
+// Power pins
+    wb_rst_i, wbs_ack_o, wbs_cyc_i,
+    wbs_stb_i, wbs_we_i, wb_clk_i,
+    wbs_adr_i, wbs_dat_i, wbs_dat_o, wbs_sel_i
+// Logic analyser pins
+    io_in, io_oeb, io_out, la_oen,
+    la_data_in, la_data_out,
+// analog_io
+    analog_io,
+// User clock
+    user_clock2);
+
+// Power pins
+input vccd1;
+input vccd2;
+input vdda1;
+input vdda2;
+input vssa1;
+input vssa2;
+input vssd1;
+input vssd2;
+// Power pins
+input wb_clk_i;
+input wb_rst_i;
+output wbs_ack_o;
+input [31:0] wbs_adr_i;
+input [31:0] wbs_dat_i;
+output [31:0] wbs_dat_o;
+input [3:0] wbs_sel_i;
+input wbs_stb_i;
+input wbs_we_i;
+input wbs_cyc_i;
+// Logic analyser pins
+input [37:0] io_in;
+output [37:0] io_oeb;
+output [37:0] io_out;
+input [127:0] la_data_in;
+output [127:0] la_data_out;
+input [127:0] la_oen;
+// Analog_pin
+inout [30:0] analog_io;
+// User clock
+input user_clock2;
+
+
+// Short all power rails/domains
+assign vcca1 = vdda2;
+assign vssa1 = vssa2;
+assign vccd2 = vdda1;
+assign vssd2 = vssa1;
+assign vccd1 = vccd2;
+assign vssd1 = vssd2;
+
+module fpga_top fpga_top_uut (
+// Power connections
+    .VDD(vccd1)
+    .VSS(vssd1)
+// Wishbone connections
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+// Logic analyser connections
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oen(la_oen),
+    .io_in(io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+// Analog ports
+    .analog_io_0_(analog_io_0_),
+    .analog_io_1_(analog_io_1_),
+    .analog_io_2_(analog_io_2_),
+    .analog_io_3_(analog_io_3_),
+    .analog_io_4_(analog_io_4_),
+    .analog_io_5_(analog_io_5_),
+    .analog_io_6_(analog_io_6_),
+    .analog_io_7_(analog_io_7_),
+    .analog_io_8_(analog_io_8_),
+    .analog_io_9_(analog_io_9_),
+    .analog_io_10_(analog_io_10_),
+    .analog_io_11_(analog_io_11_),
+    .analog_io_12_(analog_io_12_),
+    .analog_io_13_(analog_io_13_),
+    .analog_io_14_(analog_io_14_),
+    .analog_io_15_(analog_io_15_),
+    .analog_io_16_(analog_io_16_),
+    .analog_io_17_(analog_io_17_),
+    .analog_io_18_(analog_io_18_),
+    .analog_io_19_(analog_io_19_),
+    .analog_io_20_(analog_io_20_),
+    .analog_io_21_(analog_io_21_),
+    .analog_io_22_(analog_io_22_),
+    .analog_io_23_(analog_io_23_),
+    .analog_io_24_(analog_io_24_),
+    .analog_io_25_(analog_io_25_),
+    .analog_io_26_(analog_io_26_),
+    .analog_io_27_(analog_io_27_),
+    .analog_io_28_(analog_io_28_),
+    .analog_io_29_(analog_io_29_),
+    .analog_io_30_(analog_io_30_),
+// User Clock
+    .user_clock2(user_clock2)
+    ) ;
+
+endmodule

SynRepoConfig/sync_files_qlsofa_hd.csv

@@ -1,4 +1,4 @@
 SrcLoc, DestLoc
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_task/,OpenFPGA_task
 FPGA1212_QLSOFA_HD_PNR/FPGA1212_QLSOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_chd.csv

@@ -1,4 +1,4 @@
 SrcLoc, DestLoc
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_task/,OpenFPGA_task
 FPGA1212_SOFA_CHD_PNR/FPGA1212_SOFA_CHD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_SOFA_CHD_PNR/fpga_top/fpga_top_icv_in_design.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v

SynRepoConfig/sync_files_sofa_hd.csv

@@ -1,4 +1,5 @@
 SrcLoc, DestLoc
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_task/,OpenFPGA_task
 FPGA1212_SOFA_HD_PNR/FPGA1212_SOFA_HD_Verilog/SRC/,verilog/OpenFPGA_Verilog/
-FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top*.pt.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+FPGA1212_SOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v,verilog/gl/caravel_${PROJ_SUFFIX,,}_top.v
+SOFA-Chips/HDL/common/user_project_wrapper_integration.v,verilog/gl/user_project_wrapper.v