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[Testbench] Critical bug fix on the caravel testbench for and2_latch benchmark

This commit is contained in:
tangxifan 2020-12-18 16:23:50 -07:00
parent 7b2632a872
commit 9e60f62299
3 changed files with 47 additions and 37 deletions
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9
TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c
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@ -62,6 +62,15 @@ void main() {
| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
*/
/* Set up the housekeeping SPI to be connected internally so */
/* that external pin changes don't affect it. */
reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
// connect to housekeeping SPI
// Connect the housekeeping SPI to the SPI master
// so that the CSB line is not left floating. This allows
// all of the GPIO pins to be used for user functions.
// By default all the I/Os are in input mode
reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;

75
TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex
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@ -6,7 +6,7 @@
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 31
13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 31
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
@ -20,39 +20,40 @@ F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08
B7 07 00 26 93 87 07 02 13 07 20 40 98 C3 B7 07
00 26 93 87 47 02 13 07 20 40 98 C3 B7 07 00 26
93 87 87 02 13 07 20 40 98 C3 B7 07 00 26 93 87
C7 02 13 07 20 40 98 C3 B7 07 00 26 93 87 07 03
13 07 20 40 98 C3 B7 07 00 26 93 87 47 03 13 07
20 40 98 C3 B7 07 00 26 93 87 87 03 13 07 20 40
98 C3 B7 07 00 26 93 87 C7 03 13 07 20 40 98 C3
B7 07 00 26 93 87 07 04 13 07 20 40 98 C3 B7 07
00 26 93 87 47 04 13 07 20 40 98 C3 B7 07 00 26
93 87 87 04 13 07 20 40 98 C3 B7 07 00 26 93 87
07 05 13 07 20 40 98 C3 B7 07 00 26 93 87 47 05
13 07 20 40 98 C3 B7 07 00 26 93 87 87 05 13 07
20 40 98 C3 B7 07 00 26 93 87 C7 05 13 07 20 40
98 C3 B7 07 00 26 93 87 07 06 13 07 20 40 98 C3
B7 07 00 26 93 87 47 06 13 07 20 40 98 C3 B7 07
00 26 93 87 87 06 13 07 20 40 98 C3 B7 07 00 26
93 87 C7 06 13 07 20 40 98 C3 B7 07 00 26 93 87
07 07 13 07 20 40 98 C3 B7 07 00 26 93 87 47 07
13 07 20 40 98 C3 B7 07 00 26 93 87 87 07 13 07
20 40 98 C3 B7 07 00 26 93 87 07 08 13 07 20 40
98 C3 B7 07 00 26 93 87 47 08 13 07 20 40 98 C3
B7 07 00 26 93 87 87 08 13 07 20 40 98 C3 B7 07
00 26 93 87 C7 08 13 07 20 40 98 C3 B7 07 00 26
93 87 47 09 13 07 20 40 98 C3 B7 07 00 26 93 87
87 09 13 07 20 40 98 C3 B7 07 00 26 93 87 C7 09
13 07 20 40 98 C3 B7 07 00 26 93 87 07 0A 13 07
20 40 98 C3 B7 07 00 26 93 87 47 0A 13 07 20 40
98 C3 B7 07 00 26 93 87 87 0A 13 07 20 40 98 C3
B7 07 00 26 93 87 07 0B 13 07 20 40 98 C3 B7 07
00 26 93 87 47 0B 13 07 20 40 98 C3 B7 07 00 26
93 87 C7 04 09 67 13 07 87 80 98 C3 B7 07 00 26
93 87 C7 0A 09 67 13 07 87 80 98 C3 B7 07 00 26
93 87 C7 07 09 67 13 07 87 80 98 C3 B7 07 00 26
93 87 07 09 09 67 13 07 87 80 98 C3 B7 07 00 26
05 47 98 C3 01 00 B7 07 00 26 98 43 85 47 E3 0C
F7 FE 01 00 32 44 41 01 82 80 00 00
B7 07 00 24 29 67 09 07 98 C3 B7 07 00 26 93 87
07 02 13 07 20 40 98 C3 B7 07 00 26 93 87 47 02
13 07 20 40 98 C3 B7 07 00 26 93 87 87 02 13 07
20 40 98 C3 B7 07 00 26 93 87 C7 02 13 07 20 40
98 C3 B7 07 00 26 93 87 07 03 13 07 20 40 98 C3
B7 07 00 26 93 87 47 03 13 07 20 40 98 C3 B7 07
00 26 93 87 87 03 13 07 20 40 98 C3 B7 07 00 26
93 87 C7 03 13 07 20 40 98 C3 B7 07 00 26 93 87
07 04 13 07 20 40 98 C3 B7 07 00 26 93 87 47 04
13 07 20 40 98 C3 B7 07 00 26 93 87 87 04 13 07
20 40 98 C3 B7 07 00 26 93 87 07 05 13 07 20 40
98 C3 B7 07 00 26 93 87 47 05 13 07 20 40 98 C3
B7 07 00 26 93 87 87 05 13 07 20 40 98 C3 B7 07
00 26 93 87 C7 05 13 07 20 40 98 C3 B7 07 00 26
93 87 07 06 13 07 20 40 98 C3 B7 07 00 26 93 87
47 06 13 07 20 40 98 C3 B7 07 00 26 93 87 87 06
13 07 20 40 98 C3 B7 07 00 26 93 87 C7 06 13 07
20 40 98 C3 B7 07 00 26 93 87 07 07 13 07 20 40
98 C3 B7 07 00 26 93 87 47 07 13 07 20 40 98 C3
B7 07 00 26 93 87 87 07 13 07 20 40 98 C3 B7 07
00 26 93 87 07 08 13 07 20 40 98 C3 B7 07 00 26
93 87 47 08 13 07 20 40 98 C3 B7 07 00 26 93 87
87 08 13 07 20 40 98 C3 B7 07 00 26 93 87 C7 08
13 07 20 40 98 C3 B7 07 00 26 93 87 47 09 13 07
20 40 98 C3 B7 07 00 26 93 87 87 09 13 07 20 40
98 C3 B7 07 00 26 93 87 C7 09 13 07 20 40 98 C3
B7 07 00 26 93 87 07 0A 13 07 20 40 98 C3 B7 07
00 26 93 87 47 0A 13 07 20 40 98 C3 B7 07 00 26
93 87 87 0A 13 07 20 40 98 C3 B7 07 00 26 93 87
07 0B 13 07 20 40 98 C3 B7 07 00 26 93 87 47 0B
13 07 20 40 98 C3 B7 07 00 26 93 87 C7 04 09 67
13 07 87 80 98 C3 B7 07 00 26 93 87 C7 0A 09 67
13 07 87 80 98 C3 B7 07 00 26 93 87 C7 07 09 67
13 07 87 80 98 C3 B7 07 00 26 93 87 07 09 09 67
13 07 87 80 98 C3 B7 07 00 26 05 47 98 C3 01 00
B7 07 00 26 98 43 85 47 E3 0C F7 FE 01 00 32 44
41 01 82 80

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TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v.tar.gz
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