mirror of https://github.com/lnis-uofu/SOFA.git
Merge pull request #76 from lnis-uofu/xt_dev
Caravel Testbench for And2_latch benchmark
This commit is contained in:
tangxifan
GitHub
commit
894378c6a7
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@ -4015,15 +4015,15 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign Test_en_S_in = Test_en_E_in ;
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assign Test_en_W_in = Test_en_E_in ;
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assign Reset_S_in = Reset_E_in ;
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assign Reset_W_in = Reset_E_in ;
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assign Test_en_E_in = Test_en_S_in ;
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assign Test_en_E_in = Test_en_W_in ;
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assign Reset_E_in = Reset_S_in ;
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assign Reset_E_in = Reset_W_in ;
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assign prog_clk_0 = prog_clk[0] ;
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assign prog_clk_2_N_in = prog_clk_2_S_in ;
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assign prog_clk_3_S_in = prog_clk_3_N_in ;
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assign clk_2_N_in = clk_2_S_in ;
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assign clk_3_S_in = clk_3_N_in ;
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assign prog_clk_2_S_in = prog_clk_2_N_in ;
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assign prog_clk_3_N_in = prog_clk_3_S_in ;
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assign clk_2_S_in = clk_2_N_in ;
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assign clk_3_N_in = clk_3_S_in ;
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cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 (
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.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
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@ -6829,7 +6829,7 @@ wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign pReset_E_in = pReset_W_in ;
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assign pReset_W_in = pReset_E_in ;
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assign prog_clk_0 = prog_clk[0] ;
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cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 (
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@ -8937,14 +8937,14 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign pReset_E_in = pReset_W_in ;
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assign pReset_W_in = pReset_E_in ;
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assign prog_clk_0 = prog_clk[0] ;
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assign prog_clk_1_W_in = prog_clk_1_E_in ;
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assign prog_clk_2_E_in = prog_clk_2_W_in ;
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assign prog_clk_3_W_in = prog_clk_3_E_in ;
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assign clk_1_W_in = clk_1_E_in ;
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assign clk_2_E_in = clk_2_W_in ;
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assign clk_3_W_in = clk_3_E_in ;
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assign prog_clk_1_E_in = prog_clk_1_W_in ;
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assign prog_clk_2_W_in = prog_clk_2_E_in ;
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assign prog_clk_3_E_in = prog_clk_3_W_in ;
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assign clk_1_E_in = clk_1_W_in ;
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assign clk_2_W_in = clk_2_E_in ;
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assign clk_3_E_in = clk_3_W_in ;
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cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
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.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
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@ -11473,7 +11473,7 @@ wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign pReset_E_in = pReset_W_in ;
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assign pReset_W_in = pReset_E_in ;
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assign prog_clk_0 = prog_clk[0] ;
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cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
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@ -27005,8 +27005,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign pReset_S_in = pReset_E_in ;
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assign pReset_W_in = pReset_E_in ;
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assign pReset_E_in = pReset_S_in ;
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assign pReset_E_in = pReset_W_in ;
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assign prog_clk_0 = prog_clk[0] ;
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sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 (
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@ -31952,23 +31952,23 @@ assign clk_3_E_out = clk_3_E_in ;
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assign clk_3_W_out = clk_3_E_in ;
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assign clk_3_N_out = clk_3_E_in ;
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assign clk_3_S_out = clk_3_E_in ;
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assign pReset_S_in = pReset_E_in ;
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assign pReset_W_in = pReset_E_in ;
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assign pReset_E_in = pReset_S_in ;
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assign pReset_E_in = pReset_W_in ;
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assign prog_clk_0 = prog_clk[0] ;
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assign prog_clk_1_N_in = prog_clk_1_S_in ;
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assign prog_clk_2_N_in = prog_clk_2_E_in ;
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assign prog_clk_2_S_in = prog_clk_2_E_in ;
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assign prog_clk_2_W_in = prog_clk_2_E_in ;
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assign prog_clk_3_W_in = prog_clk_3_E_in ;
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assign prog_clk_3_S_in = prog_clk_3_E_in ;
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assign prog_clk_3_N_in = prog_clk_3_E_in ;
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assign clk_1_N_in = clk_1_S_in ;
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assign clk_2_N_in = clk_2_E_in ;
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assign clk_2_S_in = clk_2_E_in ;
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assign clk_2_W_in = clk_2_E_in ;
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assign clk_3_W_in = clk_3_E_in ;
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assign clk_3_S_in = clk_3_E_in ;
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assign clk_3_N_in = clk_3_E_in ;
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assign prog_clk_1_S_in = prog_clk_1_N_in ;
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assign prog_clk_2_E_in = prog_clk_2_N_in ;
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assign prog_clk_2_E_in = prog_clk_2_S_in ;
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assign prog_clk_2_E_in = prog_clk_2_W_in ;
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assign prog_clk_3_E_in = prog_clk_3_W_in ;
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assign prog_clk_3_E_in = prog_clk_3_S_in ;
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assign prog_clk_3_E_in = prog_clk_3_N_in ;
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assign clk_1_S_in = clk_1_N_in ;
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assign clk_2_E_in = clk_2_N_in ;
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assign clk_2_E_in = clk_2_S_in ;
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assign clk_2_E_in = clk_2_W_in ;
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assign clk_3_E_in = clk_3_W_in ;
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assign clk_3_E_in = clk_3_S_in ;
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assign clk_3_E_in = clk_3_N_in ;
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sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 (
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.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
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@ -36254,8 +36254,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
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supply1 VDD ;
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supply0 VSS ;
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assign pReset_S_in = pReset_E_in ;
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assign pReset_W_in = pReset_E_in ;
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assign pReset_E_in = pReset_S_in ;
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assign pReset_E_in = pReset_W_in ;
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assign prog_clk_0 = prog_clk[0] ;
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sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 (
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@ -53152,13 +53152,13 @@ wire [0:0] Test_en ;
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supply1 VDD ;
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supply0 VSS ;
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assign SC_IN_TOP = SC_IN_BOT ;
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assign Test_en_E_in = Test_en_W_in ;
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assign Reset_E_in = Reset_W_in ;
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assign SC_IN_BOT = SC_IN_TOP ;
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assign Test_en_W_in = Test_en_E_in ;
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assign Reset_W_in = Reset_E_in ;
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assign prog_clk[0] = prog_clk_0 ;
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assign prog_clk_0_N_in = prog_clk_0_S_in ;
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assign prog_clk_0_S_in = prog_clk_0_N_in ;
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assign clk_0 = clk[0] ;
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assign clk_0_N_in = clk_0_S_in ;
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assign clk_0_S_in = clk_0_N_in ;
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grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 (
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.pReset ( pReset ) ,
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@ -61,7 +61,7 @@ custom_nlist = open(args.output_verilog, "w")
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def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, add_inverter_follower):
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lines = []
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# Instanciate a 3-input MUX cell
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lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(")
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lines.append("\tsky130_uuopenfpga_fd_cc_invmux3_1 sky130_uuopenfpga_fd_cc_invmux3_1_" + str(instance_index) + "(")
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lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
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lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
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lines.append("\t .Q3(in[" + str(first_input_index + 2) + "]),")
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@ -79,7 +79,7 @@ def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, a
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# Instanciate an inverter follower to pair the MUX cells (which has input inverters)
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if (add_inverter_follower):
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lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower" + str(instance_index) + "(")
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lines.append("\tsky130_fd_sc_hd__inv_1 sky130_uuopenfpga_fd_cc_invmux3_1_inv_follower" + str(instance_index) + "(")
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lines.append("\t .A(out_inv[0]),")
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lines.append("\t .Y(out[0])")
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lines.append("\t );")
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@ -93,7 +93,7 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, a
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lines = []
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# Instanciate a 2-input MUX cell
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lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(")
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lines.append("\tsky130_uuopenfpga_fd_cc_invmux2_1 sky130_uuopenfpga_fd_cc_invmux2_1_" + str(instance_index) + "(")
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lines.append("\t .Q1(in[" + str(first_input_index) + "]),")
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lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),")
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lines.append("\t .S0(mem[" + str(first_input_index) + "]),")
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@ -108,7 +108,7 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, a
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# Instanciate an inverter follower to pair the MUX cells (which has input inverters)
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if (add_inverter_follower):
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lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower" + str(instance_index) + "(")
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lines.append("\tsky130_fd_sc_hd__inv_1 sky130_uuopenfpga_fd_cc_invmux2_1_inv_follower" + str(instance_index) + "(")
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lines.append("\t .A(out_inv[0]),")
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lines.append("\t .Y(out[0])")
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lines.append("\t );")
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@ -3,7 +3,7 @@
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// type: scs8hd_muxinv8_1
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`timescale 1ns/10ps
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`celldefine
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module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
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module sky130_uuopenfpga_cc_hd_invmux2_1 (Z, Q1, Q2, S0, S0B, S1, S1B);
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output Z;
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input Q1, Q2, S0, S0B, S1, S1B;
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@ -36,7 +36,7 @@ endmodule
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// type: scs8hd_muxinv8_1
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`timescale 1ns/10ps
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`celldefine
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module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
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module sky130_uuopenfpga_cc_hd_invmux3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B);
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output Z;
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input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B;
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@ -0,0 +1,30 @@
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FIRMWARE_PATH = ../common
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GCC_PATH?=/research/ece/lnis/USERS/DARPA_ERI/tools/riscv32i/bin
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GCC_PREFIX?=riscv32-unknown-elf
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.SUFFIXES:
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PATTERN = and2_latch_test_caravel
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all: ${PATTERN:=.hex}
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hex: ${PATTERN:=.hex}
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%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
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${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
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%.hex: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
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# to fix flash base address
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sed -i 's/@10000000/@00000000/g' $@
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%.bin: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
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# ---- Clean ----
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clean:
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rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
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.PHONY: clean hex all
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@ -0,0 +1,123 @@
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#include "../common/defs.h"
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/*
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* Scan-chain Test:
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* - Configures directions for control ports
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* +==========+===============+===========+
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* | GPIO | Functionality | Direction |
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* +==========+===============+===========+
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* | GPIO[0] | TEST_EN | input |
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* +----------+---------------+-----------+
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* | GPIO[1] | IO_ISOL_N | input |
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* +----------+---------------+-----------+
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* | GPIO[2] | RESET | input |
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* +----------+---------------+-----------+
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* | GPIO[3] | PROG_RESET | input |
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* +----------+---------------+-----------+
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* | GPIO[11] | SC_TAIL | output |
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* +----------+---------------+-----------+
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* | GPIO[12] | CCFF_HEAD | input |
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* +----------+---------------+-----------+
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* | GPIO[25] | MODE_SWITCH) | input |
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* +----------+---------------+-----------+
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* | GPIO[26] | SC_HEAD | input |
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* +----------+---------------+-----------+
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* | GPIO[35] | CCFF_TAIL | output |
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* +----------+---------------+-----------+
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* | GPIO[36] | CLK | input |
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* +----------+---------------+-----------+
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* | GPIO[37] | PROG_CLK | input |
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* +----------+---------------+-----------+
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*
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* - Configure unused FPGA data I/Os to be input
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* - Configure used FPGA data I/Os
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*
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* +==========+===============+===========+
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* | GPIO | Functionality | Direction |
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* +==========+===============+===========+
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* | GPIO[24] | a | input |
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* +----------+---------------+-----------+
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* | GPIO[27] | b | input |
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* +----------+---------------+-----------+
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* | GPIO[28] | c | output |
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* +----------+---------------+-----------+
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* | GPIO[23] | d | output |
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* +----------+---------------+-----------+
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*/
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void main() {
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/*
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IO Control Registers
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
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Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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*/
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/* Set up the housekeeping SPI to be connected internally so */
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/* that external pin changes don't affect it. */
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reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
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// connect to housekeeping SPI
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// Connect the housekeeping SPI to the SPI master
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// so that the CSB line is not left floating. This allows
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// all of the GPIO pins to be used for user functions.
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// By default all the I/Os are in input mode
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;
|
||||
// Only specify those should be in output mode
|
||||
reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
|
||||
// Implementation outputs
|
||||
reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
|
||||
/* Apply configuration */
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
@00000000
|
||||
93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
|
||||
13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
|
||||
13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
|
||||
13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00
|
||||
13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
|
||||
13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
|
||||
13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
|
||||
13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 31
|
||||
93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
|
||||
11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
|
||||
63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
|
||||
01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
|
||||
A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
|
||||
23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
|
||||
F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
|
||||
00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
|
||||
93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
|
||||
93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
|
||||
23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
|
||||
FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
|
||||
A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08
|
||||
B7 07 00 24 29 67 09 07 98 C3 B7 07 00 26 93 87
|
||||
07 02 13 07 20 40 98 C3 B7 07 00 26 93 87 47 02
|
||||
13 07 20 40 98 C3 B7 07 00 26 93 87 87 02 13 07
|
||||
20 40 98 C3 B7 07 00 26 93 87 C7 02 13 07 20 40
|
||||
98 C3 B7 07 00 26 93 87 07 03 13 07 20 40 98 C3
|
||||
B7 07 00 26 93 87 47 03 13 07 20 40 98 C3 B7 07
|
||||
00 26 93 87 87 03 13 07 20 40 98 C3 B7 07 00 26
|
||||
93 87 C7 03 13 07 20 40 98 C3 B7 07 00 26 93 87
|
||||
07 04 13 07 20 40 98 C3 B7 07 00 26 93 87 47 04
|
||||
13 07 20 40 98 C3 B7 07 00 26 93 87 87 04 13 07
|
||||
20 40 98 C3 B7 07 00 26 93 87 07 05 13 07 20 40
|
||||
98 C3 B7 07 00 26 93 87 47 05 13 07 20 40 98 C3
|
||||
B7 07 00 26 93 87 87 05 13 07 20 40 98 C3 B7 07
|
||||
00 26 93 87 C7 05 13 07 20 40 98 C3 B7 07 00 26
|
||||
93 87 07 06 13 07 20 40 98 C3 B7 07 00 26 93 87
|
||||
47 06 13 07 20 40 98 C3 B7 07 00 26 93 87 87 06
|
||||
13 07 20 40 98 C3 B7 07 00 26 93 87 C7 06 13 07
|
||||
20 40 98 C3 B7 07 00 26 93 87 07 07 13 07 20 40
|
||||
98 C3 B7 07 00 26 93 87 47 07 13 07 20 40 98 C3
|
||||
B7 07 00 26 93 87 87 07 13 07 20 40 98 C3 B7 07
|
||||
00 26 93 87 07 08 13 07 20 40 98 C3 B7 07 00 26
|
||||
93 87 47 08 13 07 20 40 98 C3 B7 07 00 26 93 87
|
||||
87 08 13 07 20 40 98 C3 B7 07 00 26 93 87 C7 08
|
||||
13 07 20 40 98 C3 B7 07 00 26 93 87 47 09 13 07
|
||||
20 40 98 C3 B7 07 00 26 93 87 87 09 13 07 20 40
|
||||
98 C3 B7 07 00 26 93 87 C7 09 13 07 20 40 98 C3
|
||||
B7 07 00 26 93 87 07 0A 13 07 20 40 98 C3 B7 07
|
||||
00 26 93 87 47 0A 13 07 20 40 98 C3 B7 07 00 26
|
||||
93 87 87 0A 13 07 20 40 98 C3 B7 07 00 26 93 87
|
||||
07 0B 13 07 20 40 98 C3 B7 07 00 26 93 87 47 0B
|
||||
13 07 20 40 98 C3 B7 07 00 26 93 87 C7 04 09 67
|
||||
13 07 87 80 98 C3 B7 07 00 26 93 87 C7 0A 09 67
|
||||
13 07 87 80 98 C3 B7 07 00 26 93 87 C7 07 09 67
|
||||
13 07 87 80 98 C3 B7 07 00 26 93 87 07 09 09 67
|
||||
13 07 87 80 98 C3 B7 07 00 26 05 47 98 C3 01 00
|
||||
B7 07 00 26 98 43 85 47 E3 0C F7 FE 01 00 32 44
|
||||
41 01 82 80
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,8 @@
|
|||
`timescale 1 ns / 1 ps
|
||||
|
||||
`define POWER_UP_TIME_PERIOD 200
|
||||
`define SOC_SETUP_TIME_PERIOD 2000
|
||||
`define SOC_RESET_TIME_PERIOD 2000
|
||||
`define SOC_SETUP_TIME_PERIOD 200*2001
|
||||
`define SOC_CLOCK_PERIOD 12.5
|
||||
`define FPGA_PROG_CLOCK_PERIOD 12.5
|
||||
`define FPGA_CLOCK_PERIOD 12.5
|
||||
|
|
@ -180,7 +181,7 @@ module ccff_test_post_pnr_caravel_autocheck_top_tb;
|
|||
initial begin
|
||||
RSTB <= 1'b0;
|
||||
soc_setup_done <= 1'b1;
|
||||
#(`SOC_SETUP_TIME_PERIOD);
|
||||
#(`SOC_RESET_TIME_PERIOD);
|
||||
RSTB <= 1'b1; // Release reset
|
||||
soc_setup_done <= 1'b1; // We can start scff test
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,7 +1,8 @@
|
|||
`timescale 1 ns / 1 ps
|
||||
|
||||
`define POWER_UP_TIME_PERIOD 200
|
||||
`define SOC_SETUP_TIME_PERIOD 2000
|
||||
`define SOC_RESET_TIME_PERIOD 2000
|
||||
`define SOC_SETUP_TIME_PERIOD 200*2001
|
||||
`define SOC_CLOCK_PERIOD 12.5
|
||||
`define FPGA_CLOCK_PERIOD 12.5
|
||||
|
||||
|
|
@ -177,7 +178,7 @@ module scff_test_post_pnr_caravel_autocheck_top_tb;
|
|||
initial begin
|
||||
RSTB <= 1'b0;
|
||||
soc_setup_done <= 1'b1;
|
||||
#(`SOC_SETUP_TIME_PERIOD);
|
||||
#(`SOC_RESET_TIME_PERIOD);
|
||||
RSTB <= 1'b1; // Release reset
|
||||
soc_setup_done <= 1'b1; // We can start scff test
|
||||
end
|
||||
|
|
|
|||
BIN
TESTBENCH/common/scff_test_post_pnr_v1.1.v (Stored with Git LFS)
BIN
TESTBENCH/common/scff_test_post_pnr_v1.1.v (Stored with Git LFS)
Binary file not shown.
|
|
@ -0,0 +1,18 @@
|
|||
//-------------------------------------------
|
||||
// A file to include all the dependency HDL codes
|
||||
// required by Caravel gate-level netlists
|
||||
//-------------------------------------------
|
||||
//----- Time scale -----
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
// Design parameter for FPGA bitstream sizes
|
||||
`define FPGA_BITSTREAM_SIZE 78765
|
||||
|
||||
// Include caravel gate-level netlists
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v"
|
||||
|
||||
`include "and2_latch_output_verilog.v"
|
||||
|
||||
// Include testbench files
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v"
|
||||
|
|
@ -14,15 +14,28 @@
|
|||
// Design parameter for FPGA bitstream sizes
|
||||
`define FPGA_SCANCHAIN_SIZE 2304
|
||||
|
||||
`define USE_POWER_PINS 1
|
||||
|
||||
// ------ Include simulation defines -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v"
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
`ifndef USE_POWER_PINS
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v"
|
||||
`endif
|
||||
|
||||
// ------ Include Skywater cell netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
`ifndef USE_POWER_PINS
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v"
|
||||
`else
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
|
||||
`endif
|
||||
|
||||
// ------ Include fabric top-level netlists -----
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
`ifndef USE_POWER_PINS
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v"
|
||||
`else
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v"
|
||||
`endif
|
||||
|
||||
`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v"
|
||||
|
|
|
|||
Loading…
Reference in New Issue