From 187364ebc3ad2801ba0fe777b52553ab81cb1b57 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Dec 2020 20:19:12 -0700 Subject: [PATCH 01/13] [Testbench] Add Caravel testbench for and2_testbench --- TESTBENCH/caravel_dv/and2_latch_test/Makefile | 30 +++++ .../and2_latch_test/and2_latch_test_caravel.c | 114 ++++++++++++++++++ .../and2_latch_test_caravel.hex | 58 +++++++++ .../and2_latch_test_caravel.v.tar.gz | Bin 0 -> 2090858 bytes 4 files changed, 202 insertions(+) create mode 100644 TESTBENCH/caravel_dv/and2_latch_test/Makefile create mode 100644 TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c create mode 100755 TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex create mode 100644 TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v.tar.gz diff --git a/TESTBENCH/caravel_dv/and2_latch_test/Makefile b/TESTBENCH/caravel_dv/and2_latch_test/Makefile new file mode 100644 index 0000000..fa25fc2 --- /dev/null +++ b/TESTBENCH/caravel_dv/and2_latch_test/Makefile @@ -0,0 +1,30 @@ +FIRMWARE_PATH = ../common + +GCC_PATH?=/research/ece/lnis/USERS/DARPA_ERI/tools/riscv32i/bin +GCC_PREFIX?=riscv32-unknown-elf + +.SUFFIXES: + +PATTERN = and2_latch_test_caravel + +all: ${PATTERN:=.hex} + +hex: ${PATTERN:=.hex} + +%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s + ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $< + +%.hex: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@ + # to fix flash base address + sed -i 's/@10000000/@00000000/g' $@ + +%.bin: %.elf + ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@ + +# ---- Clean ---- + +clean: + rm -f *.elf *.hex *.bin *.vvp *.vcd *.log + +.PHONY: clean hex all diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c new file mode 100644 index 0000000..59a82b6 --- /dev/null +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c @@ -0,0 +1,114 @@ +#include "../common/defs.h" + +/* + * Scan-chain Test: + * - Configures directions for control ports + * +==========+===============+===========+ + * | GPIO | Functionality | Direction | + * +==========+===============+===========+ + * | GPIO[0] | TEST_EN | input | + * +----------+---------------+-----------+ + * | GPIO[1] | IO_ISOL_N | input | + * +----------+---------------+-----------+ + * | GPIO[2] | RESET | input | + * +----------+---------------+-----------+ + * | GPIO[3] | PROG_RESET | input | + * +----------+---------------+-----------+ + * | GPIO[11] | SC_TAIL | output | + * +----------+---------------+-----------+ + * | GPIO[12] | CCFF_HEAD | input | + * +----------+---------------+-----------+ + * | GPIO[25] | MODE_SWITCH) | input | + * +----------+---------------+-----------+ + * | GPIO[26] | SC_HEAD | input | + * +----------+---------------+-----------+ + * | GPIO[35] | CCFF_TAIL | output | + * +----------+---------------+-----------+ + * | GPIO[36] | CLK | input | + * +----------+---------------+-----------+ + * | GPIO[37] | PROG_CLK | input | + * +----------+---------------+-----------+ + * + * - Configure unused FPGA data I/Os to be input + * - Configure used FPGA data I/Os + * + * +==========+===============+===========+ + * | GPIO | Functionality | Direction | + * +==========+===============+===========+ + * | GPIO[24] | a | input | + * +----------+---------------+-----------+ + * | GPIO[27] | b | input | + * +----------+---------------+-----------+ + * | GPIO[28] | c | output | + * +----------+---------------+-----------+ + * | GPIO[23] | d | output | + * +----------+---------------+-----------+ + +*/ + +void main() { + /* + IO Control Registers + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | + + Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | + + + Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL + | DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN | + | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | + + */ + + // By default all the I/Os are in input mode + reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL; + reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL; + // Only specify those should be in output mode + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT; + + // Implementation outputs + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT; + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + +} + diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex new file mode 100755 index 0000000..89aa53d --- /dev/null +++ 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00:00:00 2001 From: tangxifan Date: Thu, 17 Dec 2020 20:20:39 -0700 Subject: [PATCH 02/13] [Testbench] Add include netlist for caravel testbench --- ...2_latch_post_pnr_caravel_include_netlists.v | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_caravel_include_netlists.v diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_caravel_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_caravel_include_netlists.v new file mode 100644 index 0000000..c7c9f39 --- /dev/null +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/and2_latch_post_pnr_caravel_include_netlists.v @@ -0,0 +1,18 @@ +//------------------------------------------- +// A file to include all the dependency HDL codes +// required by Caravel gate-level netlists +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA bitstream sizes +`define FPGA_BITSTREAM_SIZE 78765 + +// Include caravel gate-level netlists +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/caravel_qlsofa_hd_rtl_include_netlists.v" + +`include "and2_latch_output_verilog.v" + +// Include testbench files +`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v" +`include "/research/ece/lnis/USERS/tang/github/caravel/verilog/dv/caravel/spiflash.v" From f258cefd9a89c8c52c8b88e679f91b823496ef00 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 10:55:17 -0700 Subject: [PATCH 03/13] [QLSOFA-HD] Patch on lvs netlist --- .../fpga_top/fpga_top_icv_in_design.lvs.v | 84 +++++++++---------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v index 87c2891..c372496 100644 --- a/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v +++ b/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v @@ -4015,15 +4015,15 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign Test_en_S_in = Test_en_E_in ; -assign Test_en_W_in = Test_en_E_in ; -assign Reset_S_in = Reset_E_in ; -assign Reset_W_in = Reset_E_in ; +assign Test_en_E_in = Test_en_S_in ; +assign Test_en_E_in = Test_en_W_in ; +assign Reset_E_in = Reset_S_in ; +assign Reset_E_in = Reset_W_in ; assign prog_clk_0 = prog_clk[0] ; -assign prog_clk_2_N_in = prog_clk_2_S_in ; -assign prog_clk_3_S_in = prog_clk_3_N_in ; -assign clk_2_N_in = clk_2_S_in ; -assign clk_3_S_in = clk_3_N_in ; +assign prog_clk_2_S_in = prog_clk_2_N_in ; +assign prog_clk_3_N_in = prog_clk_3_S_in ; +assign clk_2_S_in = clk_2_N_in ; +assign clk_3_N_in = clk_3_S_in ; cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 ( .in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] , @@ -6829,7 +6829,7 @@ wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign pReset_E_in = pReset_W_in ; +assign pReset_W_in = pReset_E_in ; assign prog_clk_0 = prog_clk[0] ; cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 ( @@ -8937,14 +8937,14 @@ wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign pReset_E_in = pReset_W_in ; +assign pReset_W_in = pReset_E_in ; assign prog_clk_0 = prog_clk[0] ; -assign prog_clk_1_W_in = prog_clk_1_E_in ; -assign prog_clk_2_E_in = prog_clk_2_W_in ; -assign prog_clk_3_W_in = prog_clk_3_E_in ; -assign clk_1_W_in = clk_1_E_in ; -assign clk_2_E_in = clk_2_W_in ; -assign clk_3_W_in = clk_3_E_in ; +assign prog_clk_1_E_in = prog_clk_1_W_in ; +assign prog_clk_2_W_in = prog_clk_2_E_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign clk_1_E_in = clk_1_W_in ; +assign clk_2_W_in = clk_2_E_in ; +assign clk_3_E_in = clk_3_W_in ; cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( .in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] , @@ -11473,7 +11473,7 @@ wire [0:0] logical_tile_io_mode_io__7_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign pReset_E_in = pReset_W_in ; +assign pReset_W_in = pReset_E_in ; assign prog_clk_0 = prog_clk[0] ; cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 ( @@ -27005,8 +27005,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign pReset_S_in = pReset_E_in ; -assign pReset_W_in = pReset_E_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; assign prog_clk_0 = prog_clk[0] ; sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 ( @@ -31952,23 +31952,23 @@ assign clk_3_E_out = clk_3_E_in ; assign clk_3_W_out = clk_3_E_in ; assign clk_3_N_out = clk_3_E_in ; assign clk_3_S_out = clk_3_E_in ; -assign pReset_S_in = pReset_E_in ; -assign pReset_W_in = pReset_E_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; assign prog_clk_0 = prog_clk[0] ; -assign prog_clk_1_N_in = prog_clk_1_S_in ; -assign prog_clk_2_N_in = prog_clk_2_E_in ; -assign prog_clk_2_S_in = prog_clk_2_E_in ; -assign prog_clk_2_W_in = prog_clk_2_E_in ; -assign prog_clk_3_W_in = prog_clk_3_E_in ; -assign prog_clk_3_S_in = prog_clk_3_E_in ; -assign prog_clk_3_N_in = prog_clk_3_E_in ; -assign clk_1_N_in = clk_1_S_in ; -assign clk_2_N_in = clk_2_E_in ; -assign clk_2_S_in = clk_2_E_in ; -assign clk_2_W_in = clk_2_E_in ; -assign clk_3_W_in = clk_3_E_in ; -assign clk_3_S_in = clk_3_E_in ; -assign clk_3_N_in = clk_3_E_in ; +assign prog_clk_1_S_in = prog_clk_1_N_in ; +assign prog_clk_2_E_in = prog_clk_2_N_in ; +assign prog_clk_2_E_in = prog_clk_2_S_in ; +assign prog_clk_2_E_in = prog_clk_2_W_in ; +assign prog_clk_3_E_in = prog_clk_3_W_in ; +assign prog_clk_3_E_in = prog_clk_3_S_in ; +assign prog_clk_3_E_in = prog_clk_3_N_in ; +assign clk_1_S_in = clk_1_N_in ; +assign clk_2_E_in = clk_2_N_in ; +assign clk_2_E_in = clk_2_S_in ; +assign clk_2_E_in = clk_2_W_in ; +assign clk_3_E_in = clk_3_W_in ; +assign clk_3_E_in = clk_3_S_in ; +assign clk_3_E_in = clk_3_N_in ; sb_1__1__mux_tree_tapbuf_size11_0 mux_top_track_0 ( .in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] , @@ -36254,8 +36254,8 @@ wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ; supply1 VDD ; supply0 VSS ; -assign pReset_S_in = pReset_E_in ; -assign pReset_W_in = pReset_E_in ; +assign pReset_E_in = pReset_S_in ; +assign pReset_E_in = pReset_W_in ; assign prog_clk_0 = prog_clk[0] ; sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 ( @@ -53152,13 +53152,13 @@ wire [0:0] Test_en ; supply1 VDD ; supply0 VSS ; -assign SC_IN_TOP = SC_IN_BOT ; -assign Test_en_E_in = Test_en_W_in ; -assign Reset_E_in = Reset_W_in ; +assign SC_IN_BOT = SC_IN_TOP ; +assign Test_en_W_in = Test_en_E_in ; +assign Reset_W_in = Reset_E_in ; assign prog_clk[0] = prog_clk_0 ; -assign prog_clk_0_N_in = prog_clk_0_S_in ; +assign prog_clk_0_S_in = prog_clk_0_N_in ; assign clk_0 = clk[0] ; -assign clk_0_N_in = clk_0_S_in ; +assign clk_0_S_in = clk_0_N_in ; grid_clb_logical_tile_clb_mode_clb_ logical_tile_clb_mode_clb__0 ( .pReset ( pReset ) , From 2b0294e40a6d098464ad4c90e693dbc85d3de15d Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 15:39:00 -0700 Subject: [PATCH 04/13] [Testbench] Recover from LFS --- TESTBENCH/common/scff_test_post_pnr_v1.1.v | 202 ++++++++++++++++++++- 1 file changed, 199 insertions(+), 3 deletions(-) diff --git a/TESTBENCH/common/scff_test_post_pnr_v1.1.v b/TESTBENCH/common/scff_test_post_pnr_v1.1.v index 1b1a7b1..d4dc16c 100644 --- a/TESTBENCH/common/scff_test_post_pnr_v1.1.v +++ b/TESTBENCH/common/scff_test_post_pnr_v1.1.v @@ -1,3 +1,199 @@ -version https://git-lfs.github.com/spec/v1 -oid sha256:dcad9b2185f4571e82799aca46235e4193c3744c41b4ed6507ea2f339c9d894a -size 5872 +//------------------------------------------- +// Verilog Testbench for Verifying +// Scan Chain of a FPGA +// Description: This test is applicable to FPGAs which have a built-in scan +// chain. It will feed a pulse to the head of the scan chain and +// check if the pulse is outputted by the tail of the can chain +// in a given time period +// +// Note: This test bench is tuned for the pre PnR netlists +// Author: Xifan TANG +// Organization: University of Utah +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +// Design parameter for FPGA I/O sizes +//`define FPGA_IO_SIZE 144 +// +// Design parameter for FPGA scan-chain sizes +//`define FPGA_SCANCHAIN_SIZE 2304 + +module scff_test_post_pnr_autocheck_top_tb; +// ----- Local wires for global ports of FPGA fabric ----- +wire [0:0] pReset; +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] clk; +wire [0:0] Reset; + +// ----- Local wires for I/Os of FPGA fabric ----- + +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_IN; +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT; +wire [0:`FPGA_IO_SIZE - 1] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR; + +reg [0:0] prog_clock_reg; +wire [0:0] prog_clock; +wire [0:0] op_clock; +reg [0:0] op_clock_reg; +reg [0:0] prog_reset; +reg [0:0] prog_set; +reg [0:0] greset; +reg [0:0] gset; +// ---- Configuration-chain head ----- +wire [0:0] ccff_head; +// ---- Configuration-chain tail ----- +wire [0:0] ccff_tail; + +// ---- Scan-chain head ----- +reg [0:0] sc_head; +// ---- Scan-chain tail ----- +wire [0:0] sc_tail; + +wire [0:0] IO_ISOL_N; + +// ----- Counters for error checking ----- +integer num_clock_cycles = 0; +integer num_errors = 0; +integer num_checked_points = 0; + +// Indicate when configuration should be finished +reg scan_done = 0; + +initial + begin + scan_done = 1'b0; + end + +// ----- Begin raw programming clock signal generation ----- +initial + begin + prog_clock_reg[0] = 1'b0; + end +// ----- End raw programming clock signal generation ----- + +// ----- Begin raw operating clock signal generation ----- +initial + begin + op_clock_reg[0] = 1'b0; + end +always + begin + #5 op_clock_reg[0] = ~op_clock_reg[0]; + end + +// ----- End raw operating clock signal generation ----- +// ----- Actual operating clock is triggered only when scan_done is enabled ----- + assign prog_clock[0] = prog_clock_reg[0] & ~greset; + assign op_clock[0] = op_clock_reg[0] & ~greset; + +// ----- Begin programming reset signal generation ----- +initial + begin + prog_reset[0] = 1'b0; + end + +// ----- End programming reset signal generation ----- + +// ----- Begin programming set signal generation ----- +initial + begin + prog_set[0] = 1'b0; + end + +// ----- End programming set signal generation ----- + +// ----- Begin operating reset signal generation ----- +// ----- Reset signal is disabled always ----- +initial + begin + greset[0] = 1'b1; + #10 greset[0] = 1'b0; + end + +// ----- End operating reset signal generation ----- +// ----- Begin operating set signal generation: always disabled ----- +initial + begin + gset[0] = 1'b0; + end + +// ----- End operating set signal generation: always disabled ----- + +// ----- Begin connecting global ports of FPGA fabric to stimuli ----- + assign clk[0] = op_clock[0]; + assign prog_clk[0] = prog_clock[0]; + assign pReset[0] = ~prog_reset[0]; + assign Reset[0] = ~greset[0]; + assign Test_en[0] = ~greset; + assign ccff_head[0] = 1'b0; + assign IO_ISOL_N[0] = 1'b0; +// ----- End connecting global ports of FPGA fabric to stimuli ----- +// ----- FPGA top-level module to be capsulated ----- + fpga_core FPGA_DUT ( + .pReset(pReset[0]), + .prog_clk(prog_clk[0]), + .Test_en(Test_en[0]), + .clk(clk[0]), + .Reset(Reset[0]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_IN(gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_OUT(gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1]), + .gfpga_pad_EMBEDDED_IO_HD_SOC_DIR(gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0:`FPGA_IO_SIZE - 1]), + .ccff_head(ccff_head[0]), + .ccff_tail(ccff_tail[0]), + .sc_head(sc_head[0]), + .sc_tail(sc_tail[0]), + .IO_ISOL_N(IO_ISOL_N) + ); + +// ----- Force constant '0' to FPGA I/O as this testbench only check +// programming phase ----- + assign gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}}; + assign gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0:`FPGA_IO_SIZE - 1] = {`FPGA_IO_SIZE {1'b0}}; + +// Generate a pulse after operating reset is disabled (in the 2nd clock +// cycle). Then the head of scan chain should be always zero + always @(negedge op_clock[0]) begin + sc_head = 1'b1; + if (0 != num_clock_cycles) begin + sc_head = 1'b0; + end + end + +// ----- Count the number of programming cycles ------- + always @(posedge op_clock[0]) begin + num_clock_cycles = num_clock_cycles + 1; + // Indicate when scan chain loading is suppose to end + if (`FPGA_SCANCHAIN_SIZE + 1 == num_clock_cycles) begin + scan_done = 1'b1; + end + + // Check the tail of scan-chain when configuration is done + if (1'b1 == scan_done) begin + // The tail should spit a pulse after configuration is done + // So it should be at logic '1' and then pulled down to logic '0' + if (0 == num_checked_points) begin + if (sc_tail !== 1'b1) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + if (1 <= num_checked_points) begin + if (sc_tail !== 1'b0) begin + $display("Error: sc_tail = %b", sc_tail); + num_errors = num_errors + 1; + end + end + num_checked_points = num_checked_points + 1; + end + + if (2 < num_checked_points) begin + $display("Simulation finish with %d errors", num_errors); + + // End simulation + $finish; + end + end + +endmodule From 7b2632a8727990c66dd369b6690b3bd6c8ca8132 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 15:55:05 -0700 Subject: [PATCH 05/13] [Testbench] Add power pin support to scff testbench --- TESTBENCH/common/scff_test_post_pnr_v1.1.v | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/TESTBENCH/common/scff_test_post_pnr_v1.1.v b/TESTBENCH/common/scff_test_post_pnr_v1.1.v index d4dc16c..065e08a 100644 --- a/TESTBENCH/common/scff_test_post_pnr_v1.1.v +++ b/TESTBENCH/common/scff_test_post_pnr_v1.1.v @@ -144,6 +144,10 @@ initial .ccff_tail(ccff_tail[0]), .sc_head(sc_head[0]), .sc_tail(sc_tail[0]), +`ifdef USE_POWER_PINS + .VDD(1'b1), + .VSS(1'b0), +`endif .IO_ISOL_N(IO_ISOL_N) ); From 9e60f62299a347b15dddcbab5173a0d6b0d7cb5f Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 16:23:50 -0700 Subject: [PATCH 06/13] [Testbench] Critical bug fix on the caravel testbench for and2_latch benchmark --- .../and2_latch_test/and2_latch_test_caravel.c | 9 +++ .../and2_latch_test_caravel.hex | 75 +++++++++--------- .../and2_latch_test_caravel.v.tar.gz | Bin 2090858 -> 2090859 bytes 3 files changed, 47 insertions(+), 37 deletions(-) diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c index 59a82b6..14d79e1 100644 --- a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.c @@ -62,6 +62,15 @@ void main() { | 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | */ + /* Set up the housekeeping SPI to be connected internally so */ + /* that external pin changes don't affect it. */ + reg_spimaster_config = 0xa002; // Enable, prescaler = 2, + // connect to housekeeping SPI + // Connect the housekeeping SPI to the SPI master + // so that the CSB line is not left floating. This allows + // all of the GPIO pins to be used for user functions. + + // By default all the I/Os are in input mode reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL; diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex index 89aa53d..fd1f90b 100755 --- a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex @@ -6,7 +6,7 @@ 13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00 13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00 13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00 -13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 45 31 +13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 C5 31 93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1 11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00 63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28 @@ -20,39 +20,40 @@ F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F 23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F 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z3+uI-{H?_-QUb|OI9wYpZlhs>2kr?NHarnC66I9kU`IFg!+d-^J;$ou{xmkq))^Uz z>ZV%7JH#6Y+z~%@2r5n)p<0RR<;1@Vc6sn8bBZX`3i~|z#JNx=k9CY!9ZxdK_T3}0 zW=sre4Nj_)?ufqBhKQNHDz-u|7lxSCrzZ+0b@DR;#Qaw6bPmI`>590I)g>18O%_JE z(~Sbg1~6e1Ly!}d!{{9dw-?7XnPSk%7}QRi=Q&WDR;*0N&e zn9R+>>JuvL?OK~ACr=FX;_~1<`)inx^VHp`jMrGx#`3&x`zALcd45uT86lNf|x}SMLORLGDxI#QUFYF@|o%I{pl`S0b<94-=5v?rAzT5#m*V;!=pY>flDL{0hl-Eve+TYW+;uE=!t14X1 z9(GL`sF8i z?nQ<^L!Z=ipL~vfvxOJ_Y9dA)BnW`WQirQirCJs7ak-|9K)b;F0aBX^5ySMcu~0o` zf~}kQc}x7^?s{kD zH$vdQ>fVZ1!e1vHjhZd9v}!u_!V_%CV~58hL*3uPC!6{CUzWyHw8{#59Ymd<6Exf~ zYRlxRKwbV&S%PV{02`8X$0ozWvo8B$Rc}8NEy-QI;n%`7;&Sumxnto8d4_@!eql+> zfYM0on5uZV!YaWO^BZ&GxrwCUyYhk#3dNTs>iO722%H#QBMzvz!Wb)wO7g|}vp%uh zgYG_ZOT|2f6RR2H_a;M|urDXCHi_CUJ}Vz29k)3nP$gi$W1da=0w-g2(GPlaS$%R; zF?%qCArf_|4zpTo6Iz5lzD&jhGn^_a$ZI0y2o&5gN=tyi=`+zTFn}|VFd%v~z{v@4 z7q1aLDr;iA%ogmbU)q(@?`ECRBjQ@PzwhYeRZzuU0}P@b*3A%g(VDcl98(6bRbWl( zWn;Bb?yV%uOC&1f&hr!ZSr2>^P-zw%LDOepSq!z6G0CNpVqL?d902tv3u|w)g+vll zByB3DLEv44zE(GM{_7vOxsva>n)MDsE=P*O0{wmeHz=5 l-Az9y*eJ51m~;~~DZ9D}ib@A3ip0|IcD1&Dx7I@T{{TTN4Z8pU From f028437fefab519e12d24b4bc20c6338d4d96e7c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 16:24:56 -0700 Subject: [PATCH 07/13] [Testbench] Update SCFF test to be compatible with simulation with power pins --- .../scff_test_post_pnr_include_netlists.v | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 24708c9..72bdd92 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -14,15 +14,28 @@ // Design parameter for FPGA bitstream sizes `define FPGA_SCANCHAIN_SIZE 2304 +`define USE_POWER_PINS 1 + // ------ Include simulation defines ----- `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/prepnr/verilog_testbench/define_simulation.v" -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/HDL/common/skywater_function_verification.v" +`endif // ------ Include Skywater cell netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/post_pnr_fpga_cells.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/PDK/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v" +`endif // ------ Include fabric top-level netlists ----- -`include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`ifndef USE_POWER_PINS + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`endif `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v" From e17d51aa9f759ac78db3dc1a1cae1b18a0bfab29 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 17:49:16 -0700 Subject: [PATCH 08/13] [Testbench] Bug fix in using power pins --- .../verilog_testbench/scff_test_post_pnr_include_netlists.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v index 72bdd92..930469b 100644 --- a/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v +++ b/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_12x12_fdhd_cc/postpnr/verilog_testbench/scff_test_post_pnr_include_netlists.v @@ -33,9 +33,9 @@ // ------ Include fabric top-level netlists ----- `ifndef USE_POWER_PINS - `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" -`else `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.pt.v" +`else + `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/FPGA1212_QLSOFA_HD_PNR/fpga_top/fpga_top_icv_in_design.lvs.v" `endif `include "/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/common/scff_test_post_pnr_v1.1.v" From 03316d6e6552237eed3d2f6b1d2d57a0b4078d93 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 19:51:54 -0700 Subject: [PATCH 09/13] [Testbench] Remove signal initialization which is not neccessary for caravel tests --- .../and2_latch_test/and2_latch_test_caravel.v | 79135 ++++++++++++++++ 1 file changed, 79135 insertions(+) create mode 100644 TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v new file mode 100644 index 0000000..7587835 --- /dev/null +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v @@ -0,0 +1,79135 @@ +//------------------------------------------- +// FPGA Synthesizable Verilog Netlist +// Description: FPGA Verilog Testbench for Top-level netlist of Design: and2_latch +// Author: Xifan TANG +// Organization: University of Utah +// Date: Wed Dec 2 17:58:35 2020 +//------------------------------------------- +//----- Time scale ----- +`timescale 1ns / 1ps + +`define POWER_UP_TIME_PERIOD 200 +`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_CLOCK_PERIOD 12.5 +`define FPGA_PROG_CLOCK_PERIOD 12.5 +`define FPGA_CLOCK_PERIOD 12.5 + +module and2_latch_post_pnr_caravel_autocheck_top_tb; + reg clock; + reg RSTB; + reg power1, power2; + reg power3, power4; + + wire gpio; + wire [37:0] mprj_io; + + reg soc_setup_done; + +// ----- Local wires for global ports of FPGA fabric ----- +wire [0:0] pReset; +wire [0:0] prog_clk; +wire [0:0] Test_en; +wire [0:0] IO_ISOL_N; +wire [0:0] clk; +wire [0:0] Reset; + +// ----- Local wires for I/Os of FPGA fabric ----- + +reg [0:0] config_done; +wire [0:0] prog_clock; +reg [0:0] prog_clock_reg; +wire [0:0] op_clock; +reg [0:0] op_clock_reg; +reg [0:0] prog_reset; +reg [0:0] prog_set; +reg [0:0] greset; +reg [0:0] gset; +// ---- Configuration-chain head ----- +reg [0:0] ccff_head; +// ---- Configuration-chain tail ----- +wire [0:0] ccff_tail; +// ---- Scan-chain head ---- +wire [0:0] sc_head; +// ---- Scan-chain tail ---- +wire [0:0] sc_tail; +// ----- Shared inputs ------- + reg [0:0] a; + reg [0:0] b; + +// ----- FPGA fabric outputs ------- + wire [0:0] out_c_fpga; + wire [0:0] out_d_fpga; + +// ----- Benchmark outputs ------- + wire [0:0] out_c_benchmark; + wire [0:0] out_d_benchmark; + +// ----- Output vectors checking flags ------- + reg [0:0] out_c_flag; + reg [0:0] out_d_flag; + +// ----- Error counter: Deposit an error for config_done signal is not raised at the beginning ----- + integer nb_error= 1; +// ----- Number of clock cycles in configuration phase: 78766 ----- +// ----- Begin configuration done signal generation ----- +initial + begin + config_done[0] = 1'b0; + end + +// ----- End configuration done signal generation ----- + +// ----- Begin raw programming clock signal generation ----- +initial + begin + prog_clock_reg[0] = 1'b0; + end +always + begin + #(`FPGA_PROG_CLOCK_PERIOD) prog_clock_reg[0] = ~prog_clock_reg[0]; + end + +// ----- End raw programming clock signal generation ----- + +// ----- Actual programming clock is triggered only when config_done and prog_reset are disabled ----- + assign prog_clock[0] = prog_clock_reg[0] & (~config_done[0]) & (~prog_reset[0]); + +// ----- Begin raw operating clock signal generation ----- +initial + begin + op_clock_reg[0] = 1'b0; + end +always wait(~greset) + begin + #(`FPGA_CLOCK_PERIOD) op_clock_reg[0] = ~op_clock_reg[0]; + end + +// ----- End raw operating clock signal generation ----- +// ----- Actual operating clock is triggered only when config_done is enabled ----- + assign op_clock[0] = op_clock_reg[0] & config_done[0]; + +// ----- Begin programming reset signal generation ----- +initial + begin + prog_reset[0] = 1'b1; + #(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_reset[0] = 1'b0; + end + +// ----- End programming reset signal generation ----- + +// ----- Begin programming set signal generation ----- +initial + begin + prog_set[0] = 1'b1; + #(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_set[0] = 1'b0; + end + +// ----- End programming set signal generation ----- + +// ----- Begin operating reset signal generation ----- +// ----- Reset signal is enabled until the first clock cycle in operation phase ----- +initial + begin + greset[0] = 1'b1; + wait(config_done) + #(`FPGA_CLOCK_PERIOD*2) greset[0] = 1'b1; + #(`FPGA_CLOCK_PERIOD*4) greset[0] = 1'b0; + end + +// ----- End operating reset signal generation ----- +// ----- Begin operating set signal generation: always disabled ----- +initial + begin + gset[0] = 1'b0; + end + +// ----- End operating set signal generation: always disabled ----- + +// ----- Begin connecting global ports of FPGA fabric to stimuli ----- + assign prog_clk[0] = prog_clock[0]; + assign clk[0] = op_clock[0]; + assign pReset[0] = ~prog_reset[0]; + assign Reset[0] = ~greset[0]; + assign Test_en[0] = 1'b0; + assign IO_ISOL_N[0] = 1'b1; + assign sc_head[0] = 1'b0; +// ----- End connecting global ports of FPGA fabric to stimuli ----- +// + assign mprj_io[0] = Test_en; + assign mprj_io[1] = IO_ISOL_N; + assign mprj_io[2] = Reset; + assign mprj_io[3] = pReset; + assign mprj_io[12] = ccff_head; + assign mprj_io[25] = 1'b0; // Set FPGA to interface logic analyzer by default + assign mprj_io[26] = sc_head; + assign mprj_io[36] = clk; + assign mprj_io[37] = prog_clk; + + assign sc_tail = mprj_io[11]; + assign ccff_tail = mprj_io[35]; + + assign mprj_io[10:4] = {7{1'b0}}; + assign mprj_io[22:13] = {10{1'b0}}; + assign mprj_io[34:29] = {6{1'b0}}; + + assign mprj_io[24] = a[0]; + assign mprj_io[27] = b[0]; + + assign out_c_fpga[0] = mprj_io[28]; + assign out_d_fpga[0] = mprj_io[23]; + +// ----- Reference Benchmark Instanication ------- + and2_latch REF_DUT( + .a(a), + .b(b), + .clk(clk), + .c(out_c_benchmark), + .d(out_d_benchmark) ); +// ----- End reference Benchmark Instanication ------- + + +// ----- Task: input values during a programming clock cycle ----- +task prog_cycle_task; +input [0:0] ccff_head_val; + begin + @(negedge prog_clock[0]); + ccff_head[0] = ccff_head_val[0]; + end +endtask + +// ----- Begin bitstream loading during configuration phase ----- +initial + begin +// ----- Configuration chain default input ----- + ccff_head[0] = 1'b0; + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + 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prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b1); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + prog_cycle_task(1'b0); + @(negedge prog_clock[0]); + config_done[0] <= 1'b1; + end +// ----- End bitstream loading during configuration phase ----- + +// ----- Input Initialization ------- + initial begin + a <= 1'b0; + b <= 1'b0; + + out_c_flag[0] <= 1'b0; + out_d_flag[0] <= 1'b0; + end + +// ----- Input Stimulus ------- + always@(negedge op_clock[0]) begin + a <= $random; + b <= $random; + end + +// ----- Begin checking output vectors ------- +// ----- Skip the first falling edge of clock, it is for initialization ------- + reg [0:0] sim_start; + + always@(negedge clk[0]) begin + if (1'b1 == sim_start[0]) begin + sim_start[0] <= ~sim_start[0]; + end else begin + if(!(out_c_fpga === out_c_benchmark) && !(out_c_benchmark === 1'bx)) begin + out_c_flag <= 1'b1; + end else begin + out_c_flag<= 1'b0; + end + if(!(out_d_fpga === out_d_benchmark) && !(out_d_benchmark === 1'bx)) begin + out_d_flag <= 1'b1; + end else begin + out_d_flag<= 1'b0; + end + end + end + + always@(posedge out_c_flag) begin + if(out_c_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on out_c_fpga at time = %t", $realtime); + end + end + + always@(posedge out_d_flag) begin + if(out_d_flag) begin + nb_error = nb_error + 1; + $display("Mismatch on out_d_fpga at time = %t", $realtime); + end + end + +// ----- Configuration done must be raised in the end ------- + always@(posedge config_done[0]) begin + nb_error = nb_error - 1; + end + +`ifdef ICARUS_SIMULATOR +// ----- Begin Icarus requirement ------- + initial begin + $dumpfile("and2_latch_formal.vcd"); + $dumpvars(1, and2_latch_autocheck_top_tb); + end +`endif +// ----- END Icarus requirement ------- + +initial begin + sim_start[0] <= 1'b1; + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); +// ----- Can be changed by the user for his/her need ------- + #((`FPGA_BITSTREAM_SIZE + 3)* `FPGA_PROG_CLOCK_PERIOD * 2 + `SOC_SETUP_TIME_PERIOD + 20 * `FPGA_CLOCK_PERIOD) + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; +end + + // External clock is used by default. Make this artificially fast for the + // simulation. Normally this would be a slow clock and the digital PLL + // would be the fast clock. + + always #(`SOC_CLOCK_PERIOD) clock <= (clock === 1'b0); + + initial begin + clock = 0; + end + + initial begin + RSTB <= 1'b0; + soc_setup_done <= 1'b1; + #(`SOC_SETUP_TIME_PERIOD); + RSTB <= 1'b1; // Release reset + soc_setup_done <= 1'b1; // We can start scff test + end + + initial begin // Power-up sequence + power1 <= 1'b0; + power2 <= 1'b0; + power3 <= 1'b0; + power4 <= 1'b0; + #(`POWER_UP_TIME_PERIOD); + power1 <= 1'b1; + #(`POWER_UP_TIME_PERIOD); + power2 <= 1'b1; + #(`POWER_UP_TIME_PERIOD); + power3 <= 1'b1; + #(`POWER_UP_TIME_PERIOD); + power4 <= 1'b1; + end + + wire flash_csb; + wire flash_clk; + wire flash_io0; + wire flash_io1; + + wire VDD3V3 = power1; + wire VDD1V8 = power2; + wire USER_VDD3V3 = power3; + wire USER_VDD1V8 = power4; + wire VSS = 1'b0; + + caravel uut ( + .vddio (VDD3V3), + .vssio (VSS), + .vdda (VDD3V3), + .vssa (VSS), + .vccd (VDD1V8), + .vssd (VSS), + .vdda1 (USER_VDD3V3), + .vdda2 (USER_VDD3V3), + .vssa1 (VSS), + .vssa2 (VSS), + .vccd1 (USER_VDD1V8), + .vccd2 (USER_VDD1V8), + .vssd1 (VSS), + .vssd2 (VSS), + .clock (clock), + .gpio (gpio), + .mprj_io (mprj_io), + .flash_csb(flash_csb), + .flash_clk(flash_clk), + .flash_io0(flash_io0), + .flash_io1(flash_io1), + .resetb (RSTB) + ); + + spiflash #( + .FILENAME("/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.hex") + ) spiflash ( + .csb(flash_csb), + .clk(flash_clk), + .io0(flash_io0), + .io1(flash_io1), + .io2(), // not used + .io3() // not used + ); + + +endmodule +// ----- END Verilog module for and2_latch_autocheck_top_tb ----- From 8a31edb40e4d7101471069e4364c21524030005e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 19:52:52 -0700 Subject: [PATCH 10/13] [Testbench] Remove compressed testbench file --- .../and2_latch_test_caravel.v.tar.gz | Bin 2090859 -> 0 bytes 1 file changed, 0 insertions(+), 0 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zIuEgHbxnW%ysp2El*9{4Zn6qfc>*hF`d) zM>?86C~{IV%oy!Xey<`&KTq)BGyR)PG@`R-kCf9!i(VM&*YRyKIeUg3nJwXlBxiPu zYy*FoKsYYN;NJ~+L5vvvtDG>Ops(ZMwX%V)Wa#C}>KF(N)vT3o&+bv@w?#)Akoe5* z(*F8UiGIN-D_>om;WPUBPMYEHVAozgJ8Cw$Csfs(!GC)^rI0?d!L;5=(Aa7mOa8E# zBbO#-Cg>Tub+xyFx2N3xcXs&xg7D=p%k}5)+i7usuj=2If3AM+o*qB{&Y!KXCl{Ts vef=%-&-{CTKfdcPuix|g@m=}%|0=#8-))auXw8@Y|LnhO)|4_BxU&HOwf+qU From 1eac22feba4bf644a336c514262ffea7acad023c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 20:18:02 -0700 Subject: [PATCH 11/13] [Testbench] Critical bug fix on Caravel Testbench: Add a sufficient long waiting time for Caravel to finish its I/O configuration --- .../caravel_dv/and2_latch_test/and2_latch_test_caravel.v | 5 +++-- TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v | 5 +++-- TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v index 7587835..2cf870e 100644 --- a/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v +++ b/TESTBENCH/caravel_dv/and2_latch_test/and2_latch_test_caravel.v @@ -9,7 +9,8 @@ `timescale 1ns / 1ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_PROG_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -79063,7 +79064,7 @@ end initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end diff --git a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v index 955a177..41065bc 100644 --- a/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v +++ b/TESTBENCH/caravel_dv/ccff_test/ccff_test_caravel.v @@ -1,7 +1,8 @@ `timescale 1 ns / 1 ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_PROG_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -180,7 +181,7 @@ module ccff_test_post_pnr_caravel_autocheck_top_tb; initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end diff --git a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v index 97dd641..f846520 100644 --- a/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v +++ b/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.v @@ -1,7 +1,8 @@ `timescale 1 ns / 1 ps `define POWER_UP_TIME_PERIOD 200 -`define SOC_SETUP_TIME_PERIOD 2000 +`define SOC_RESET_TIME_PERIOD 2000 +`define SOC_SETUP_TIME_PERIOD 200*2001 `define SOC_CLOCK_PERIOD 12.5 `define FPGA_CLOCK_PERIOD 12.5 @@ -177,7 +178,7 @@ module scff_test_post_pnr_caravel_autocheck_top_tb; initial begin RSTB <= 1'b0; soc_setup_done <= 1'b1; - #(`SOC_SETUP_TIME_PERIOD); + #(`SOC_RESET_TIME_PERIOD); RSTB <= 1'b1; // Release reset soc_setup_done <= 1'b1; // We can start scff test end From c523d968c715395f53ae5a4ca7b8b36a9ab03a3c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 20:24:55 -0700 Subject: [PATCH 12/13] [HDL] Bug fix due to custom cell name changing --- HDL/common/fd_hd_mux_custom_cells_tt.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/HDL/common/fd_hd_mux_custom_cells_tt.v b/HDL/common/fd_hd_mux_custom_cells_tt.v index 8bde7c8..6a1035a 100644 --- a/HDL/common/fd_hd_mux_custom_cells_tt.v +++ b/HDL/common/fd_hd_mux_custom_cells_tt.v @@ -3,7 +3,7 @@ // type: scs8hd_muxinv8_1 `timescale 1ns/10ps `celldefine -module scs8hd_muxinv2_1 (Z, Q1, Q2, S0, S0B, S1, S1B); +module sky130_uuopenfpga_cc_hd_invmux2_1 (Z, Q1, Q2, S0, S0B, S1, S1B); output Z; input Q1, Q2, S0, S0B, S1, S1B; @@ -36,7 +36,7 @@ endmodule // type: scs8hd_muxinv8_1 `timescale 1ns/10ps `celldefine -module scs8hd_muxinv3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B); +module sky130_uuopenfpga_cc_hd_invmux3_1 (Z, Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B); output Z; input Q1, Q2, Q3, S0, S0B, S1, S1B, S2, S2B; From 82da5dd0b0bbaa93f89572bcff6d3a7740da1741 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 18 Dec 2020 20:25:50 -0700 Subject: [PATCH 13/13] [HDL] Update code generator for the changes on custom cell names --- HDL/common/custom_cell_mux_primitive_generator.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/HDL/common/custom_cell_mux_primitive_generator.py b/HDL/common/custom_cell_mux_primitive_generator.py index 39099a9..bfb0edc 100644 --- a/HDL/common/custom_cell_mux_primitive_generator.py +++ b/HDL/common/custom_cell_mux_primitive_generator.py @@ -61,7 +61,7 @@ custom_nlist = open(args.output_verilog, "w") def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, add_inverter_follower): lines = [] # Instanciate a 3-input MUX cell - lines.append("\tscs8hd_muxinv3_1 scs8hd_muxinv3_1_" + str(instance_index) + "(") + lines.append("\tsky130_uuopenfpga_fd_cc_invmux3_1 sky130_uuopenfpga_fd_cc_invmux3_1_" + str(instance_index) + "(") lines.append("\t .Q1(in[" + str(first_input_index) + "]),") lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") lines.append("\t .Q3(in[" + str(first_input_index + 2) + "]),") @@ -79,7 +79,7 @@ def generate_verilog_codes_custom_cell_mux3(first_input_index, instance_index, a # Instanciate an inverter follower to pair the MUX cells (which has input inverters) if (add_inverter_follower): - lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv3_1_inv_follower" + str(instance_index) + "(") + lines.append("\tsky130_fd_sc_hd__inv_1 sky130_uuopenfpga_fd_cc_invmux3_1_inv_follower" + str(instance_index) + "(") lines.append("\t .A(out_inv[0]),") lines.append("\t .Y(out[0])") lines.append("\t );") @@ -93,7 +93,7 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, a lines = [] # Instanciate a 2-input MUX cell - lines.append("\tscs8hd_muxinv2_1 scs8hd_muxinv2_1_" + str(instance_index) + "(") + lines.append("\tsky130_uuopenfpga_fd_cc_invmux2_1 sky130_uuopenfpga_fd_cc_invmux2_1_" + str(instance_index) + "(") lines.append("\t .Q1(in[" + str(first_input_index) + "]),") lines.append("\t .Q2(in[" + str(first_input_index + 1) + "]),") lines.append("\t .S0(mem[" + str(first_input_index) + "]),") @@ -108,7 +108,7 @@ def generate_verilog_codes_custom_cell_mux2(first_input_index, instance_index, a # Instanciate an inverter follower to pair the MUX cells (which has input inverters) if (add_inverter_follower): - lines.append("\tsky130_fd_sc_hd__inv_1 scs8hd_muxinv2_1_inv_follower" + str(instance_index) + "(") + lines.append("\tsky130_fd_sc_hd__inv_1 sky130_uuopenfpga_fd_cc_invmux2_1_inv_follower" + str(instance_index) + "(") lines.append("\t .A(out_inv[0]),") lines.append("\t .Y(out[0])") lines.append("\t );")

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