mirror of https://github.com/lnis-uofu/SOFA.git
incoporated changes based on feedback from xifan
This commit is contained in:
Tarachand Pagarani
parent
01fabc65cc
commit
1aa0ef68e4
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@ -417,6 +417,7 @@
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<direct name="direct2" input="fabric.sc_in" output="ff.DI"/>
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<direct name="direct4" input="ff.Q" output="fabric.sc_out"/>
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<direct name="direct5" input="ff.Q" output="fabric.reg_out"/>
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<direct name="direct6" input="frac_logic.cout" output="fabric.cout"/>
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<complete name="complete1" input="fabric.clk" output="ff.clk"/>
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<complete name="complete2" input="fabric.reset" output="ff.reset"/>
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<mux name="mux1" input="frac_logic.out fabric.reg_in" output="ff.D">
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@ -125,22 +125,7 @@
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I0" num_pins="2" equivalent="full"/>
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<input name="I0i" num_pins="2" equivalent="none"/>
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<input name="I1" num_pins="2" equivalent="full"/>
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<input name="I1i" num_pins="2" equivalent="none"/>
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<input name="I2" num_pins="2" equivalent="full"/>
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<input name="I2i" num_pins="2" equivalent="none"/>
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<input name="I3" num_pins="2" equivalent="full"/>
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<input name="I3i" num_pins="2" equivalent="none"/>
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<input name="I4" num_pins="2" equivalent="full"/>
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<input name="I4i" num_pins="2" equivalent="none"/>
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<input name="I5" num_pins="2" equivalent="full"/>
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<input name="I5i" num_pins="2" equivalent="none"/>
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<input name="I6" num_pins="2" equivalent="full"/>
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<input name="I6i" num_pins="2" equivalent="none"/>
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<input name="I7" num_pins="2" equivalent="full"/>
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<input name="I7i" num_pins="2" equivalent="none"/>
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<input name="I" num_pins="24" equivalent="full"/>
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<input name="reg_in" num_pins="1"/>
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<input name="sc_in" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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@ -163,8 +148,8 @@
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<!--pinlocations pattern="spread"/-->
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<pinlocations pattern="custom">
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<loc side="left">clb.clk clb.reset</loc>
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<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i</loc>
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<loc side="right">clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i</loc>
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<loc side="top">clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I[11:0]</loc>
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<loc side="right">clb.O[15:8] clb.I[23:12]</loc>
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<loc side="bottom">clb.reg_out clb.sc_out clb.cout</loc>
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</pinlocations>
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</tile>
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@ -349,22 +334,7 @@
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So pin equivalence should be applied to the first 3 inputs only
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-->
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<pb_type name="clb">
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<input name="I0" num_pins="2" equivalent="full"/>
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<input name="I0i" num_pins="2" equivalent="none"/>
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<input name="I1" num_pins="2" equivalent="full"/>
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<input name="I1i" num_pins="2" equivalent="none"/>
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<input name="I2" num_pins="2" equivalent="full"/>
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<input name="I2i" num_pins="2" equivalent="none"/>
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<input name="I3" num_pins="2" equivalent="full"/>
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<input name="I3i" num_pins="2" equivalent="none"/>
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<input name="I4" num_pins="2" equivalent="full"/>
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<input name="I4i" num_pins="2" equivalent="none"/>
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<input name="I5" num_pins="2" equivalent="full"/>
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<input name="I5i" num_pins="2" equivalent="none"/>
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<input name="I6" num_pins="2" equivalent="full"/>
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<input name="I6i" num_pins="2" equivalent="none"/>
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<input name="I7" num_pins="2" equivalent="full"/>
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<input name="I7i" num_pins="2" equivalent="none"/>
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<input name="I" num_pins="24" equivalent="full"/>
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<input name="reg_in" num_pins="1"/>
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<input name="sc_in" num_pins="1"/>
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<input name="cin" num_pins="1"/>
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@ -648,55 +618,10 @@
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<!-- FIXME: The implicit port definition results in I0[0] connected to
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in[2]. Such twisted connection is not expected.
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I[0] should be connected to in[0]
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-->
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<direct name="direct_fle0" input="clb.I0[0:1]" output="fle[0:0].in[0:1]">
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-->
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<complete name="crossbar" input="clb.I fle[7:0].out" output="fle[7:0].in">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle0i" input="clb.I0i[0:1]" output="fle[0:0].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle1" input="clb.I1[0:1]" output="fle[1:1].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle1i" input="clb.I1i[0:1]" output="fle[1:1].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle2" input="clb.I2[0:1]" output="fle[2:2].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle2i" input="clb.I2i[0:1]" output="fle[2:2].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle3" input="clb.I3[0:1]" output="fle[3:3].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle3i" input="clb.I3i[0:1]" output="fle[3:3].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle4" input="clb.I4[0:1]" output="fle[4:4].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle4i" input="clb.I4i[0:1]" output="fle[4:4].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle5" input="clb.I5[0:1]" output="fle[5:5].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle5i" input="clb.I5i[0:1]" output="fle[5:5].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle6" input="clb.I6[0:1]" output="fle[6:6].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle6i" input="clb.I6i[0:1]" output="fle[6:6].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle7" input="clb.I7[0:1]" output="fle[7:7].in[0:1]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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<direct name="direct_fle7i" input="clb.I7i[0:1]" output="fle[7:7].in[2:3]">
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<!-- TODO: Timing should be backannotated from post-PnR results -->
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</direct>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[7:0].clk">
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</complete>
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<complete name="resets" input="clb.reset" output="fle[7:0].reset">
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@ -1,48 +0,0 @@
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# This script is designed to generate fabric Verilog netlists
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# with a fixed device layout
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# It will only output netlists to be used by backend tools,
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# i.e., Synopsys ICC2, including
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# - Verilog netlists
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# - fabric hierarchy description for ICC2's hierarchical flow
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# - Timing/Design constraints
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#
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
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# Write the fabric hierarchy of module graph to a file
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# This is used by hierarchical PnR flows
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write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1
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# Write the Verilog netlist for FPGA fabric
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# - Enable the use of explicit port mapping in Verilog netlist
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# which is required by Synopsys ICC2 parser
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write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \
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--explicit_port_mapping \
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--verbose
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -1,37 +0,0 @@
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# This script is designed to generate fabric Verilog netlists
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# with a fixed device layout
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# It will only output netlists to be used by backend tools,
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# i.e., Synopsys ICC2, including
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# - Verilog netlists
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# - fabric hierarchy description for ICC2's hierarchical flow
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# - Timing/Design constraints
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#
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
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# Write the SDC files for PnR backend
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# - Turn on every options here
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write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR}
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# Write SDC to disable timing for configure ports
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write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -1,74 +0,0 @@
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# This script is designed to generate Verilog testbenches
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# with a fixed device layout
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# It will only output netlists to be used by verification tools
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# including
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# - Verilog testbenches, used by ModelSim
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# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime
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#
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#--write_rr_graph example_rr_graph.xml
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vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off
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# Read OpenFPGA architecture definition
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read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
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# Read OpenFPGA simulation settings
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read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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# Annotate the OpenFPGA architecture to VPR data base
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# to debug use --verbose options
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link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
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# Check and correct any naming conflicts in the BLIF netlist
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check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
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# Apply fix-up to clustering nets based on routing results
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pb_pin_fixup --verbose
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# Apply fix-up to Look-Up Table truth tables based on packing results
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lut_truth_table_fixup
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# Build the module graph
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# - Enabled compression on routing architecture modules
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# - Enable pin duplication on grid modules
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build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose
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# Repack the netlist to physical pbs
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# This must be done before bitstream generator and testbench generation
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# Strongly recommend it is done after all the fix-up have been applied
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repack #--verbose
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# Build the bitstream
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# - Output the fabric-independent bitstream to a file
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build_architecture_bitstream --verbose --write_file arch_bitstream.xml
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# Build fabric-dependent bitstream
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build_fabric_bitstream --verbose
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# Write fabric-dependent bitstream
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write_fabric_bitstream --file fabric_bitstream.xml --format xml
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# Write the Verilog testbench for FPGA fabric
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# - We suggest the use of same output directory as fabric Verilog netlists
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# - Must specify the reference benchmark file if you want to output any testbenches
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# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
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# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
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# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
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write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \
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--fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \
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--reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \
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--print_top_testbench \
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--print_preconfig_top_testbench \
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--print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \
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--explicit_port_mapping
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# Exclude signal initialization since it does not help simulator converge
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# due to the lack of reset pins for flip-flops
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#--include_signal_init
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# Write the SDC to run timing analysis for a mapped FPGA fabric
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write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis
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# Finish and exit OpenFPGA
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exit
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# Note :
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# To run verification at the end of the flow maintain source in ./SRC directory
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@ -16,14 +16,14 @@ timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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openfpga_vpr_device_layout=32x32
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openfpga_vpr_route_chan_width=60
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openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
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openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
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[ARCHITECTURES]
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arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -16,13 +16,13 @@ timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga
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openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga
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openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
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openfpga_vpr_device_layout=32x32
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openfpga_vpr_route_chan_width=60
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openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
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external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
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[ARCHITECTURES]
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arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
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@ -16,14 +16,14 @@ timeout_each_job = 1*60
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fpga_flow=yosys_vpr
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[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga
|
||||
openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga
|
||||
openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=32x32
|
||||
openfpga_vpr_route_chan_width=60
|
||||
openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr
|
||||
openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v
|
||||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml
|
||||
external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
|
||||
|
|
|
|||
Loading…
Reference in New Issue