From 1aa0ef68e4afba538c55d81dc48d1eddb4398d38 Mon Sep 17 00:00:00 2001 From: Tarachand Pagarani Date: Thu, 24 Dec 2020 23:05:47 -0800 Subject: [PATCH] incoporated changes based on feedback from xifan --- ...n_chain_nonLR_caravel_io_skywater130nm.xml | 1 + ...n_chain_nonLR_caravel_io_skywater130nm.xml | 89 ++----------------- ...c_using_random_key_example_script.openfpga | 48 ---------- ...c_using_random_key_example_script.openfpga | 37 -------- ...h_using_random_key_example_script.openfpga | 74 --------------- .../generate_fabric/config/task_template.conf | 4 +- .../generate_sdc/config/task_template.conf | 4 +- .../config/task_template.conf | 4 +- 8 files changed, 14 insertions(+), 247 deletions(-) delete mode 100644 SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga delete mode 100644 SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga delete mode 100644 SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga diff --git a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 1d47257..989e4bc 100644 --- a/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -417,6 +417,7 @@ + diff --git a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml index 3696107..cb28159 100644 --- a/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml +++ b/ARCH/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -125,22 +125,7 @@ - - - - - - - - - - - - - - - - + @@ -163,8 +148,8 @@ clb.clk clb.reset - clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i - clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.reg_in clb.sc_in clb.cin clb.O[7:0] clb.I[11:0] + clb.O[15:8] clb.I[23:12] clb.reg_out clb.sc_out clb.cout @@ -349,22 +334,7 @@ So pin equivalence should be applied to the first 3 inputs only --> - - - - - - - - - - - - - - - - + @@ -648,55 +618,10 @@ - + --> + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga deleted file mode 100644 index c5ca8e5..0000000 --- a/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga +++ /dev/null @@ -1,48 +0,0 @@ -# This script is designed to generate fabric Verilog netlists -# with a fixed device layout -# It will only output netlists to be used by backend tools, -# i.e., Synopsys ICC2, including -# - Verilog netlists -# - fabric hierarchy description for ICC2's hierarchical flow -# - Timing/Design constraints -# -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose - -# Write the fabric hierarchy of module graph to a file -# This is used by hierarchical PnR flows -write_fabric_hierarchy --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/fabric_hierarchy.txt --depth 1 - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -# which is required by Synopsys ICC2 parser -write_fabric_verilog --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/SRC \ - --explicit_port_mapping \ - --verbose - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga deleted file mode 100644 index 9937c0e..0000000 --- a/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga +++ /dev/null @@ -1,37 +0,0 @@ -# This script is designed to generate fabric Verilog netlists -# with a fixed device layout -# It will only output netlists to be used by backend tools, -# i.e., Synopsys ICC2, including -# - Verilog netlists -# - fabric hierarchy description for ICC2's hierarchical flow -# - Timing/Design constraints -# -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file ${OPENFPGA_SDC_OUTPUT_DIR} - -# Write SDC to disable timing for configure ports -write_sdc_disable_timing_configure_ports --file ${OPENFPGA_SDC_OUTPUT_DIR}/disable_configure_ports.sdc - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga b/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga deleted file mode 100644 index 072c740..0000000 --- a/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga +++ /dev/null @@ -1,74 +0,0 @@ -# This script is designed to generate Verilog testbenches -# with a fixed device layout -# It will only output netlists to be used by verification tools -# including -# - Verilog testbenches, used by ModelSim -# - SDC for a mapped FPGA fabric, used by Synopsys PrimeTime -# -#--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --absorb_buffer_luts off - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} - -# Read OpenFPGA simulation settings -read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} - -# Annotate the OpenFPGA architecture to VPR data base -# to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --generate_random_fabric_key #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --write_file arch_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write fabric-dependent bitstream -write_fabric_bitstream --file fabric_bitstream.xml --format xml - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/verilog_testbench \ - --fabric_netlist_file_path ${OPENFPGA_FABRIC_VERILOG_NETLIST} \ - --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} \ - --print_top_testbench \ - --print_preconfig_top_testbench \ - --print_simulation_ini ${OPENFPGA_VERILOG_OUTPUT_DIR}/SimulationDeck/simulation_deck.ini \ - --explicit_port_mapping -# Exclude signal initialization since it does not help simulator converge -# due to the lack of reset pins for flip-flops -#--include_signal_init - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file ${OPENFPGA_VERILOG_OUTPUT_DIR}/sdc_analysis - -# Finish and exit OpenFPGA -exit - -# Note : -# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf index b9f99be..e4d0a80 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_fabric/config/task_template.conf @@ -16,14 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_random_key_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_fabric_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=32x32 openfpga_vpr_route_chan_width=60 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf index c2902b0..fbf216c 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_sdc/config/task_template.conf @@ -16,13 +16,13 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_random_key_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_sdc_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=32x32 openfpga_vpr_route_chan_width=60 openfpga_sdc_output_dir=${SKYWATER_OPENFPGA_HOME}/SDC/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf index 6bf2eea..4b45220 100644 --- a/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf +++ b/SCRIPT/skywater_openfpga_task/k4_N8_reset_softadder_caravel_cc_fdhd_32x32/generate_testbench/config/task_template.conf @@ -16,14 +16,14 @@ timeout_each_job = 1*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_random_key_example_script.openfpga +openfpga_shell_template=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_shell_script/skywater_generate_testbench_using_key_example_script.openfpga openfpga_arch_file=${SKYWATER_OPENFPGA_HOME}/ARCH/openfpga_arch/k4_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${SKYWATER_OPENFPGA_HOME}/SCRIPT/openfpga_simulation_setting/efpga_12x12_sim_openfpga.xml openfpga_vpr_device_layout=32x32 openfpga_vpr_route_chan_width=60 openfpga_verilog_output_dir=${SKYWATER_OPENFPGA_HOME}/TESTBENCH/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/prepnr openfpga_fabric_verilog_netlist=${SKYWATER_OPENFPGA_HOME}/HDL/k4_N8_reset_softadder_caravel_io_FPGA_32x32_fdhd_cc/SRC/fabric_netlists.v -external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_12x12.xml +external_fabric_key_file=${SKYWATER_OPENFPGA_HOME}/ARCH/fabric_key/fabric_key_32x32.xml [ARCHITECTURES] arch0=${SKYWATER_OPENFPGA_HOME}/ARCH/vpr_arch/k4_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml