tangxifan
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84d24ad075
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bug fix in pnr sdc grid writer for module paths in hierarchical view
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2020-06-11 19:31:05 -06:00 |
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tangxifan
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6aff33dd35
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add fabric hierarchy writer
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2020-06-11 19:31:04 -06:00 |
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tangxifan
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d325bede68
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add fabric bitstream writer
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2020-04-21 12:02:10 -06:00 |
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tangxifan
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07a384e440
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now use openfpga tokenizer to trim command line string in openfpga shell
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2020-04-13 11:08:31 -06:00 |
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tangxifan
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e31dc1f2f2
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openfpga shell now support continued line charactor '\'
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2020-04-07 21:27:51 -06:00 |
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tangxifan
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33315f0521
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now openfpga shell allow empty space at beginning and end of each line in script mode
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2020-04-07 20:46:45 -06:00 |
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tangxifan
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0b1c8ac139
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bug fixed in identifying the physical interconnect for pb_graph nodes
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2020-04-07 19:46:42 -06:00 |
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tangxifan
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50bb04d496
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add scan-chain test case. Debugging on the way
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2020-04-07 16:50:41 -06:00 |
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tangxifan
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6d6295ef93
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Add test cases about using standard cell mux2
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2020-04-07 11:12:47 -06:00 |
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tangxifan
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d39d7a68ce
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add test cases for using tree-like multiplexer
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2020-04-07 10:46:49 -06:00 |
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tangxifan
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6eb125ec2a
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Now cross-column/row is optional to direct annotation in OpenFPGA architecture XML
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2020-04-06 14:09:52 -06:00 |
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tangxifan
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ca45efd13d
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add testing script for the spy io
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2020-04-05 15:24:40 -06:00 |
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tangxifan
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32c74ad811
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added FPGA architecture with I/Os on the left and right sides
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2020-04-01 15:46:38 -06:00 |
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tangxifan
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07e1979498
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add architecture examples on wide memory blocks (width=2). tileable routing is working
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2020-03-28 15:41:26 -06:00 |
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tangxifan
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e601a648cc
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relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
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2020-03-27 19:07:34 -06:00 |
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tangxifan
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7c9c2451f2
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debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
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2020-03-27 16:03:42 -06:00 |
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tangxifan
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b09b051249
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add all the test cases considering tileable, carry chain, direct connection and memory blocks
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2020-03-27 13:58:35 -06:00 |
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tangxifan
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b6bdf78d95
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bug fixed for heterogeneous block instances in top module
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2020-03-24 17:39:26 -06:00 |
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tangxifan
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3958ac2494
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fix bugs in flow manager on default compress routing problems
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2020-03-22 15:26:15 -06:00 |
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tangxifan
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7b9384f3b2
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add write_gsb command to shell interface
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2020-03-21 19:40:26 -06:00 |
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tangxifan
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9a518e8bb6
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bug fixed for tileable rr_graph builder for more 4x4 fabrics
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2020-03-21 18:07:00 -06:00 |
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tangxifan
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708fda9606
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fixed a bug in using tileable routing when directlist is enabled
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2020-03-20 16:38:58 -06:00 |
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tangxifan
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9837be618d
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start debugging tile direct with micro architecture
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2020-03-20 14:52:52 -06:00 |
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tangxifan
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a0b150f12e
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adding micro architecture using adder chain
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2020-03-20 14:18:59 -06:00 |
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tangxifan
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29450f3472
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debugging multi-source lb router
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2020-03-12 20:42:41 -06:00 |
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tangxifan
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2a260a05aa
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add a microbenchmark `and_latch` to test LUTs in wired mode
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2020-03-11 10:40:59 -06:00 |
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tangxifan
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aff73bdd74
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deployed edge sorting and make it as an option to link_arch command
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2020-03-08 15:59:53 -06:00 |
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tangxifan
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3241d8bd37
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put analysis sdc writer online. Minor bug in redudant '/' to be fixed
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2020-03-02 19:54:18 -07:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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7b18f7cd09
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now the auto select number of clocks in simulation is online
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2020-02-29 13:29:16 -07:00 |
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tangxifan
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9fd184e3ab
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rm out-of-date script
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2020-02-28 15:42:18 -07:00 |
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tangxifan
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05ebd77d7d
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start debugging with micro benchmarks. Spot problem in local routing
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2020-02-28 15:41:32 -07:00 |
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tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
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b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
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fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
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13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
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tangxifan
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175bef014a
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add compact_routing hierarchy command
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2020-02-11 17:40:37 -07:00 |
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tangxifan
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ed9e038845
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add functionality of LUT truth table fix-up
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2020-02-06 17:14:29 -07:00 |
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tangxifan
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dad204674b
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done an initial version of clustering net fix-up based on routing results. Debugging on the way
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2020-02-05 21:50:52 -07:00 |
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tangxifan
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5006a4395d
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bring RRGraph object and writer online
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2020-01-31 16:39:40 -07:00 |