tangxifan
|
f586229b97
|
[test] enable rst_on_lut benchmark
|
2023-01-18 19:45:41 -08:00 |
|
tangxifan
|
b7a66705e0
|
[test] now use yosys_vpr flow; add rst_on_lut benchmark
|
2023-01-18 19:42:50 -08:00 |
|
tangxifan
|
e974e5ddf7
|
[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
|
2023-01-18 18:31:36 -08:00 |
|
tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
|
2023-01-18 18:17:14 -08:00 |
|
tangxifan
|
2c9593c1d4
|
[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
|
2023-01-15 13:09:40 -08:00 |
|
tangxifan
|
13aed6fff5
|
[test] still commment verification out
|
2023-01-15 12:17:59 -08:00 |
|
tangxifan
|
758cc7a089
|
[test] debugging
|
2023-01-15 11:44:48 -08:00 |
|
tangxifan
|
14bb76ec87
|
[test] remove verification steps for new test but leave a todo
|
2023-01-14 23:06:54 -08:00 |
|
tangxifan
|
9222d085cd
|
[test] now use local clock as one of the pins in a clock bus, but connected to global routing
|
2023-01-13 22:04:56 -08:00 |
|
tangxifan
|
26f71656de
|
[test] update pin constraints
|
2023-01-13 21:12:18 -08:00 |
|
tangxifan
|
93107c752a
|
[test] updating test case
|
2023-01-13 19:53:15 -08:00 |
|
tangxifan
|
1353577351
|
[test] added a new test to validate locally generated clocks
|
2023-01-13 16:45:30 -08:00 |
|
tangxifan
|
c7dc3ce7dc
|
[test] pass
|
2023-01-11 17:10:29 -08:00 |
|
tangxifan
|
f6f153ace4
|
[test] debugging
|
2023-01-11 17:06:31 -08:00 |
|
tangxifan
|
d5ebbeea9a
|
[test] adding a new test to show how to automate generation of bus group files
|
2023-01-11 16:59:54 -08:00 |
|
tangxifan
|
83d7ff56e1
|
[script] add dedicated testcase for source commands
|
2023-01-01 17:04:24 -08:00 |
|
tangxifan
|
d7a95a8ec2
|
[script] fixed some bugs
|
2022-12-30 18:30:52 -08:00 |
|
tangxifan
|
56a3e6e463
|
[test] reduce test size
|
2022-12-30 18:28:17 -08:00 |
|
tangxifan
|
ae11a4fbf2
|
[test] add a new test case
|
2022-12-30 18:25:15 -08:00 |
|
tangxifan
|
513f7800aa
|
[test] update golden outputs for no_cout_in_gsb testcase
|
2022-11-03 17:51:51 -07:00 |
|
tangxifan
|
a88bc2d4de
|
[test] update golden outputs for device4x4
|
2022-11-03 17:51:08 -07:00 |
|
tangxifan
|
5f74367c2e
|
[test] update golden for device1x1 no time stamp netlists
|
2022-11-03 17:48:40 -07:00 |
|
tangxifan
|
00a485cbeb
|
[test] add missing file
|
2022-10-17 19:44:25 -07:00 |
|
tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
|
tangxifan
|
8b00bfdff9
|
[test] replace hardcoded paths in task config files with relative paths
|
2022-10-17 11:55:57 -07:00 |
|
tangxifan
|
aa78981e37
|
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
|
2022-10-17 11:18:21 -07:00 |
|
tangxifan
|
b0be27b384
|
[test] add repack design constraints files
|
2022-10-13 11:22:48 -07:00 |
|
tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
|
tangxifan
|
4eaecde0b9
|
[test] add golden netlists to ensure no cout in gsb
|
2022-10-01 11:03:13 -07:00 |
|
tangxifan
|
78f30cf072
|
[test] add a new test to track the golden netlists where cout is not in GSB
|
2022-09-30 15:38:27 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
b532bca9d2
|
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |
|
tangxifan
|
36603f9772
|
Merge branch 'master' into vtr_upgrade
|
2022-09-20 21:08:06 -07:00 |
|
tangxifan
|
b8f1520367
|
[test] fixed a bug
|
2022-09-20 18:12:23 -07:00 |
|
tangxifan
|
4e254a304d
|
[test] now golden netlists have no relationship with OPENFPGA_PATH
|
2022-09-20 18:10:52 -07:00 |
|
tangxifan
|
5e23be19a5
|
[test] now the test case that generates golden netlist use a special openfpga arch file which contains no soft paths
|
2022-09-20 18:07:31 -07:00 |
|
tangxifan
|
1b0b50b928
|
[test] update golden netlist
|
2022-09-20 16:04:05 -07:00 |
|
tangxifan
|
846ca26311
|
[test] enable block usage information output when running vpr. Otherwise some testcases miss the information for QoR checks
|
2022-09-20 12:08:24 -07:00 |
|
tangxifan
|
10e86d334a
|
[test] add test cases to validate the various layouts where I/Os are in the center of the grid
|
2022-09-16 10:29:19 -07:00 |
|
tangxifan
|
330785635d
|
[test] now use a bigger fabric for the test case on custom I/O location
|
2022-09-13 17:53:33 -07:00 |
|
tangxifan
|
0d6e4e3979
|
[test] add a new example for the repack options
|
2022-09-12 16:21:49 -07:00 |
|
tangxifan
|
1ab7590603
|
[test] added a new test case to
|
2022-09-09 16:59:06 -07:00 |
|
tangxifan
|
d4523e819c
|
[test] fixed a bug
|
2022-09-08 16:55:50 -07:00 |
|
tangxifan
|
d76f3e3b6c
|
[test] fixed the bug
|
2022-09-08 16:34:23 -07:00 |
|
tangxifan
|
218e6d0a47
|
[arch] fixed syntax errors
|
2022-09-08 16:31:52 -07:00 |
|
tangxifan
|
a840aeea7a
|
[test] add a new test to validate custom I/O location syntax and deploy to basic regression tests
|
2022-09-08 16:27:11 -07:00 |
|
tangxifan
|
477e2119d7
|
[test] remove abs paths in golden outputs without time stamps
|
2022-09-06 15:24:43 -07:00 |
|
tangxifan
|
93ab992187
|
[test] update golden outputs without time stamps
|
2022-09-06 14:59:00 -07:00 |
|
tangxifan
|
561d0a6545
|
[test] add more test case to track golden outputs for representative fpga sizes
|
2022-09-06 14:04:23 -07:00 |