tangxifan
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eca2a35612
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[Script] Add route chan width option to vtr openfpga script
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2021-03-20 22:00:09 -06:00 |
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tangxifan
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9a3aff274f
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[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
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ca9a70fc88
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[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
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125e94a6b3
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[Test] Add full VTR benchmark (with most commented); ready for massive testing
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2021-03-20 21:01:18 -06:00 |
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tangxifan
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2bd8ef2af9
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[Benchmark] Patch boundtop.v with missing SPRAM module
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2021-03-20 21:00:53 -06:00 |
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tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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f3792bc6f6
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[Test] Update VTR benchmark test case to include DSP example benchmark
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2021-03-20 18:09:19 -06:00 |
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tangxifan
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477a522885
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
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1185f7b8bf
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[Script] Add a template yosys script to enable DSP mapping
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2021-03-20 17:05:30 -06:00 |
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tangxifan
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6bf4880c50
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[benchmark] Add vtr benchmark
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2021-03-17 15:24:26 -06:00 |
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tangxifan
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f9dc7c1b54
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[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
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2021-03-17 15:15:22 -06:00 |
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tangxifan
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08a86e056a
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[Test] Add vtr benchmark regression test
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2021-03-17 15:13:58 -06:00 |
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tangxifan
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7eeb35d21f
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[Script] Bug fix in yosys script to synthesis BRAM
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2021-03-17 15:12:04 -06:00 |
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tangxifan
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1976a8068f
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[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
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2021-03-17 15:11:17 -06:00 |
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tangxifan
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deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
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910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
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76113a80fa
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
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tangxifan
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e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
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d12a8a03fd
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[Test] Update test case using yosys bram parameters
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2021-03-16 19:52:17 -06:00 |
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tangxifan
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094b3e9b90
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[Script] Use parameters in template yosys script supporting BRAMs
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2021-03-16 19:51:48 -06:00 |
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tangxifan
|
cea43c2c45
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[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
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2021-03-16 18:04:31 -06:00 |
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tangxifan
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73b06256d0
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[Test] Deploy the new yosys script supporting BRAM to regression tests
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2021-03-16 16:52:59 -06:00 |
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tangxifan
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84778bd38d
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[Script] Add new yosys script to support architectures with BRAMs
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2021-03-16 16:52:18 -06:00 |
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tangxifan
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090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
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2021-03-16 16:45:57 -06:00 |
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tangxifan
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76837e02e6
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[Script] Rename yosys script supporting bram and restructure techlib files
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2021-03-16 16:16:53 -06:00 |
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tangxifan
|
e61857aa2b
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Merge branch 'master' into ganesh_dev
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2021-03-11 19:17:02 -07:00 |
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tangxifan
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366bec232c
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[Test] Now lut_adder_test passed end-of-flow verification; Deploy it to CI
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2021-03-11 15:25:48 -07:00 |
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tangxifan
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bb2a02c9ad
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[HDL] Patch the superLUT HDL code to be consistent with (qlf_k4n8_sim.v)[https://github.com/lnsharma/yosys/blob/add_qlf_k4n8_dev/techlibs/quicklogic/qlf_k4n8_cells_sim.v]
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2021-03-11 15:23:14 -07:00 |
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tangxifan
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baf162e401
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[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
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2021-03-10 22:45:19 -07:00 |
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tangxifan
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a6186db315
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[Test] Update bitstream annotation with new syntax
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2021-03-10 20:45:17 -07:00 |
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tangxifan
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7d07f5d8cb
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[Test] Update bitstream setting example with mode bit overwriting
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2021-03-10 15:34:53 -07:00 |
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tangxifan
|
b42541d84e
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[Flow] Support multiple iterations in rewriting yosys scripts
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2021-03-10 14:10:35 -07:00 |
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tangxifan
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90a00da1df
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[Script] Split rewrite yosys scripts into two runs because yosys cannot output consistent verilog files using 'design -reset'
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2021-03-10 13:56:35 -07:00 |
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tangxifan
|
d21909ad6c
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[Test] Use custom rewriting script in lut_adder test
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2021-03-10 13:48:20 -07:00 |
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tangxifan
|
0e772bc3b4
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[Script] Patch the yosys rewrite script to avoid existing blif outputs
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2021-03-10 13:47:30 -07:00 |
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tangxifan
|
7adb78b159
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[Script] Add a template yosys script with rewriting at the end
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2021-03-10 13:40:31 -07:00 |
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tangxifan
|
035043d0d8
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[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
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2021-03-10 13:36:11 -07:00 |
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tangxifan
|
5d46537b5b
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[Script] Allow users to specify custom post-synthesis verilog for simulation
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2021-03-10 11:45:55 -07:00 |
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tangxifan
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aafd87c3f9
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[Flow] Update flow-run to support custom yosys rewrite scripts
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2021-03-10 11:36:29 -07:00 |
Tarachand Pagarani
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db8ea86b2f
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update tests to use no_ff_map and remove tests that need async set/reset for now
|
2021-03-10 10:04:45 -08:00 |
|
Tarachand Pagarani
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608bd1f658
|
comment out desings that utilize local async reset/preset
|
2021-03-09 19:24:01 -08:00 |
|
Tarachand Pagarani
|
7f4c20ff33
|
comment out desings that utilize local async reset/preset
|
2021-03-09 10:37:06 -08:00 |
|
Tarachand Pagarani
|
c4b83aeaa9
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bypas ff map for quicklogic example openfpga flow till xml can support ff pb_type
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2021-03-09 00:46:40 -08:00 |
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tangxifan
|
2daa770319
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[Arch] Update openfpga architecture to include quicklogic cell sim
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2021-03-08 21:40:29 -07:00 |
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tangxifan
|
812d8c950e
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[Script] Update quicklogic's script to output correct verilog file name
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2021-03-08 21:39:44 -07:00 |
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tangxifan
|
37aa42d305
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[Test] Patch task configuration file for lut_adder_test to use correct rewrite script
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2021-03-08 21:38:51 -07:00 |
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tangxifan
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c53c41b7a5
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[Script] Fine-tune quicklogic yosys script to output correct post-synthesis verilog file
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2021-03-08 21:09:23 -07:00 |
|
tangxifan
|
131643dcc0
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[Flow] Bug fix for yosys rewrite function in openfpga flow-run script
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2021-03-08 21:08:55 -07:00 |
ganeshgore
|
b860722893
|
Fixed parameter ys_rewrite_params name bug
|
2021-03-08 10:34:39 -07:00 |