tangxifan
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fdf94cba83
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 15:28:34 -06:00 |
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tangxifan
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3cbe266c44
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[Test] Bug fix on the test case for multi-mode FF and pin constraints
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2021-07-02 15:27:27 -06:00 |
Ganesh Gore
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c67807868c
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[bugFix] Benchamrk variable declaration
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2021-07-02 15:26:39 -06:00 |
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tangxifan
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3aacce2a96
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Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
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2021-07-02 14:04:42 -06:00 |
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Ganesh Gore
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edd5be2cae
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[CI] Added testcase for benchmark variable
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2021-07-02 12:51:34 -06:00 |
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tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
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tangxifan
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5286f9ba25
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[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
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2021-07-02 11:39:00 -06:00 |
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tangxifan
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02fd2a69b3
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[Script] Add dff with active-low async reset to default yosys tech lib
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2021-07-02 11:17:43 -06:00 |
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tangxifan
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477e535344
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[HDL] Added a multi-mode FF design with configurable asynchronous reset
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2021-07-02 11:13:03 -06:00 |
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tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
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tangxifan
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0b6a9b06f5
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[Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality
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2021-07-02 10:39:07 -06:00 |
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Ganesh Gore
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1de1f2f2e2
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[FLOW] Variable in capital case
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2021-07-01 22:26:00 -06:00 |
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Ganesh Gore
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81f9dff9ff
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[Flow] Allows benchmark specific var declaraton
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2021-07-01 22:19:53 -06:00 |
ANDREW HARRIS POND
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1d281765ea
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fixed tab spacing
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2021-07-01 16:42:04 -06:00 |
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ANDREW HARRIS POND
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808821bb8c
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fixed errors
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2021-07-01 16:40:03 -06:00 |
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ANDREW HARRIS POND
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006b54c4bc
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ready for merge
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2021-07-01 15:35:39 -06:00 |
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ANDREW HARRIS POND
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8513b8a4ff
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Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
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2021-07-01 15:29:39 -06:00 |
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ANDREW HARRIS POND
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2567fbee05
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ready to merge
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2021-07-01 15:28:59 -06:00 |
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tangxifan
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04ceeefb0a
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Merge branch 'master' into verilog_testbench
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2021-07-01 14:43:26 -06:00 |
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ANDREW HARRIS POND
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db9231c225
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tests failing with initial blocks
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2021-07-01 13:52:28 -06:00 |
Andrew Pond
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fab2b069f0
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added signal gen regression test to shell script
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2021-06-30 16:18:09 -06:00 |
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tangxifan
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a898537474
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[Benchmark] Remove redundant post-synthesis netlist for ``adder_8``
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2021-06-30 15:29:13 -06:00 |
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tangxifan
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83d177b13b
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[Test] Deploy the newly added adder benchmarks to tests
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2021-06-30 15:14:24 -06:00 |
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tangxifan
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4d4577bb83
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[Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders
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2021-06-30 15:13:47 -06:00 |
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tangxifan
|
9eeec05a1f
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[Test] Bug fix
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2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
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[Test] Bug fix
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2021-06-29 18:51:28 -06:00 |
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tangxifan
|
56b0428eba
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[Misc] Bug fix
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2021-06-29 18:48:19 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
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2021-06-29 18:34:41 -06:00 |
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tangxifan
|
5f5a03f17f
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[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
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2021-06-29 18:28:38 -06:00 |
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tangxifan
|
2c1692e6dc
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[Test] Bug fix
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2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
4fb34642ca
|
[Script] Add a new example script for global tile clock running full testbench
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2021-06-29 17:53:56 -06:00 |
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tangxifan
|
9655bc35cb
|
[Script] Bug fix due to the full testbench generation changes
|
2021-06-29 17:04:19 -06:00 |
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tangxifan
|
cbea4a3cb6
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[Test] Add the test cases to regression test
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2021-06-29 16:08:22 -06:00 |
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tangxifan
|
30c2f597f2
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[Test] Added two cases to validate testbench generation without self checking
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2021-06-29 16:06:15 -06:00 |
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tangxifan
|
20faf82e64
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[Script] Rename example script
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2021-06-29 16:02:35 -06:00 |
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tangxifan
|
01391fd81e
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[Script] Added example scripts that use OpenFPGA to generate testbenches without self checking features
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2021-06-29 15:56:33 -06:00 |
|
tangxifan
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7119075253
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[Script] Remove the post-processing on ``define_simulation.v`` since it is deprecated
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2021-06-29 15:52:42 -06:00 |
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tangxifan
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75a12e55de
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[HDL] Remove the instrusive signal initialization in the configuration flip-flop HDL codes
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2021-06-29 11:40:22 -06:00 |
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tangxifan
|
b4c587f10b
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[Test] Added the new test cases to regression tests
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2021-06-27 19:58:15 -06:00 |
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tangxifan
|
6f0600e17f
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[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
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2021-06-27 19:56:01 -06:00 |
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tangxifan
|
4a623bec79
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[Script] Add example openfpga shell script to generate preconfigured fabric wrapper
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2021-06-27 19:55:40 -06:00 |
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tangxifan
|
fae5e1dfdf
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[Script] Upgrade openfpga shell script with the new option '--embed_bitstream'
|
2021-06-25 15:16:37 -06:00 |
|
tangxifan
|
477cba1c7e
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Merge branch 'master' into verilog_testbench
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2021-06-23 09:18:18 -06:00 |
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tangxifan
|
b2c30e3103
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[Test] Bug fix in mcnc openfpga shell script
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2021-06-22 16:40:24 -06:00 |
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tangxifan
|
e34fbf8ecf
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[Test] Deploy MCNC big20 to the micro benchmark regression test
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2021-06-22 16:36:04 -06:00 |
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tangxifan
|
f06017581c
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[Test] Bug fix in counter micro benchmark tests
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2021-06-22 16:33:50 -06:00 |
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tangxifan
|
0a0d10b36d
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[HDL] Bug fix in Verilog syntax
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2021-06-22 16:18:46 -06:00 |
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tangxifan
|
4421dfcbbd
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Merge branch 'master' into micro_benchmark
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2021-06-22 14:29:29 -06:00 |
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tangxifan
|
fd580bb36f
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[Script] Update script to keep back compatibility: local run directory is different only for those benchmarks sharing the same top module name
|
2021-06-22 11:45:23 -06:00 |
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tangxifan
|
0b2d6eb147
|
[Test] Add micro benchmark to a dedicated regression test
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2021-06-21 18:35:41 -06:00 |