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3,074 Commits 70 Branches 8 Tags 105 MiB
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3074 Commits

Author SHA1 Message Date
tangxifan da200658c1 [Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks 2021-01-19 17:29:59 -07:00
tangxifan 0670c2de59 [Tool] Deploy pin constraints to preconfig Verilog module generation 2021-01-19 16:56:30 -07:00
tangxifan e17a5cbbf2 [Test] Rename to pin constraint to comply with libpcf requirement 2021-01-19 15:52:51 -07:00
tangxifan ecd955124b [Lib] Add libpcf to CMakelist and bug fix 2021-01-19 15:51:14 -07:00
tangxifan 52ac7826eb [Lib] Add a library of parser/writer for pin constraint file (PCF) 2021-01-19 15:45:45 -07:00
tangxifan ab25e1af5f [Test] Add example XML for net mapping between benchmark to FPGA 2021-01-19 09:29:21 -07:00
tangxifan 17c49711d3
Merge pull request #174 from lnis-uofu/dev 
Support Design Constraints for Repack
 2021-01-17 17:41:53 -07:00
tangxifan c7f02601ab [Doc] Add repack design constraints to documentation 2021-01-17 12:59:46 -07:00
tangxifan 8c311b8282 [Tool] Bug fix in repacker for considering design constraints 2021-01-17 12:26:14 -07:00
tangxifan ea9d6bfe91 [Flow] Update the design constraint file to follow bug fix in parser 2021-01-17 10:41:01 -07:00
tangxifan 113119bd8e [Lib] Fix the bug in repack design constraint parser 2021-01-17 10:39:55 -07:00
tangxifan dd74f05a31 [Test] Add repack constraints to tests 2021-01-17 10:35:36 -07:00
tangxifan 12e0efd03e [Script] Add an example openfpga script to use repack design constraints 2021-01-17 10:33:56 -07:00
tangxifan 2efe513122 [Tool] Now repack consider design constraints; test pending 2021-01-16 21:57:17 -07:00
tangxifan d0e05b3575 [Lib] Now use pb_type in design constraints instead of physical tiles 2021-01-16 21:35:43 -07:00
tangxifan bb8e7e25c2 [Tool] Start deploying design constraints in repack engine 2021-01-16 21:27:12 -07:00
tangxifan b86adabe69 [Lib] Remove unused data storage from repack design constraints 2021-01-16 21:14:52 -07:00
tangxifan fa67517349 [Tool] Add repack design constraints to openfpga command 'repack' 2021-01-16 18:49:34 -07:00
tangxifan 706e84bb62 [Lib] Bug fix in testing program 2021-01-16 18:15:56 -07:00
tangxifan 67c54c4d3b [Lib] Bug fix in the repack design constraint lib 2021-01-16 17:34:22 -07:00
tangxifan ad7a54db1b [Tool] Add repack dc library to compilation 2021-01-16 17:20:59 -07:00
tangxifan 9d80f1ab39 [Lib] Add test program to the library of repack design constraints 2021-01-16 17:18:42 -07:00
tangxifan 03b5bcc244 [Lib] Add XML writer for repack design constraints 2021-01-16 17:15:31 -07:00
tangxifan 2a7601fb7e [Lib] Add libarchopenfpga to the dependency of librepackdesignconstraints 2021-01-16 17:14:51 -07:00
tangxifan f1bfa2ef8c [Lib] Add XML parser for repack design constraints 2021-01-16 17:03:01 -07:00
tangxifan 8be12b6e82 [Lib] Add example design constraint file 2021-01-16 16:36:10 -07:00
tangxifan a926c74ae5 [Lib] Add CMake script to compile the repack design constraint library 2021-01-16 16:35:46 -07:00
tangxifan b57dc7b898 [Lib] Add repack design constraint library 2021-01-16 16:35:13 -07:00
tangxifan 8578c1ecac [Flow] Rename the design contraint file syntax 2021-01-16 15:35:13 -07:00
tangxifan 9154cfdeec [Flow] Add comments for the design constraint file 2021-01-16 15:34:01 -07:00
tangxifan 6ab0f71896 [Test] Add an example of repack pin constraints file 2021-01-16 14:38:39 -07:00
tangxifan 4f1d815d7b
Merge pull request #173 from lnis-uofu/dev 
Support Multiple Clock Definition in Testbench and SDC Generators
 2021-01-15 16:13:46 -07:00
tangxifan b8e4675a3a [Tool] Add missing file 2021-01-15 14:48:19 -07:00
tangxifan c4d3e7c50c [Doc] Update documentation for the new XML syntax in simulation settings 2021-01-15 12:30:26 -07:00
tangxifan 87b2c1f3b8 [Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation 2021-01-15 12:01:53 -07:00
tangxifan 89f9d24d32 [Flow] Update simulation settings for multiple clock to allow unique clock port name 2021-01-15 10:35:43 -07:00
tangxifan dbed04b53b [Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI 2021-01-14 15:42:21 -07:00
tangxifan 3b5394b45f [Test] Now use dedicated simulation settings for the 4-clock architecture 2021-01-14 15:40:16 -07:00
tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers 2021-01-14 15:38:24 -07:00
tangxifan 923f3a3401 [Flow] Add an example simulation settings for a 4-clock FPGA fabric 2021-01-13 17:29:39 -07:00
Ashton Snelgrove effe86fb9e Remove pull request trigger 2021-01-13 17:16:39 -07:00
tangxifan ec587a6d46
Merge pull request #172 from lnis-uofu/dev 
Basic Support on Multi-Clock Fabric Netlist Generation and Testbench Generation
 2021-01-13 17:14:56 -07:00
Ashton Snelgrove afa55f1942 Merge remote-tracking branch 'origin/master' into github-action-optimizations 2021-01-13 17:07:54 -07:00
Ashton Snelgrove 2b705ba17a Add building a regression test image on master. 2021-01-13 17:05:55 -07:00
tangxifan 2b959290e9 [Test] Deploy multi-clock test to CI 2021-01-13 15:44:19 -07:00
tangxifan 9a906e787b [Benchmark] Add post-yosys .v file for counter 4-bit with dual clock 2021-01-13 15:43:31 -07:00
tangxifan 314e458632 [Test] Update task configuration to use post-yosys .v file in verification 2021-01-13 15:42:45 -07:00
tangxifan c5a2027f36 [Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR 2021-01-13 15:41:48 -07:00
tangxifan 7af6d7f07d [Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation 2021-01-13 15:38:44 -07:00
tangxifan 9cc9e45b4b [Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated 2021-01-13 15:13:19 -07:00