BaudouinChauviere
|
a904e4a37b
|
Update red_hat_compilation.md
|
2019-01-10 22:03:55 -08:00 |
|
BaudouinChauviere
|
568a5a0e92
|
Update ubuntu_compilation.md
|
2019-01-10 22:03:37 -08:00 |
Baudouin Chauviere
|
f3e7ae0823
|
Hot fix
|
2019-01-10 17:37:15 -07:00 |
tangxifan
|
b8187bbca5
|
fix a bug for supporting default circuit_model of LUTs and FFs
|
2019-01-10 15:10:05 -07:00 |
|
Baudouin Chauviere
|
9c8444da43
|
update of the examples supplied to get the right paths
|
2019-01-10 00:06:20 -07:00 |
|
Baudouin Chauviere
|
4ae3aa517c
|
go.sh replaces the paths now
|
2019-01-09 23:16:43 -07:00 |
|
Baudouin Chauviere
|
510c27f816
|
Removed commercial scripts, replaced by academia ones
|
2019-01-09 11:56:07 -07:00 |
|
Baudouin Chauviere
|
3b4fc16c60
|
Adding help message on the go.sh
|
2019-01-09 11:54:28 -07:00 |
|
tangxifan
|
66701838ff
|
update relative path in ARCH XML
|
2019-01-08 11:41:24 -07:00 |
AurelienUoU
|
b80e435548
|
Correct manual testbench generation bug
|
2019-01-07 18:03:56 -07:00 |
|
BaudouinChauviere
|
5dbcfa6d70
|
Repair broken link
|
2019-01-03 18:26:30 +01:00 |
|
BaudouinChauviere
|
28010f6c91
|
Testing another link method
|
2019-01-03 18:24:06 +01:00 |
Laboratory for Nano Integrated Systems (LNIS)
|
30f2ada557
|
Repaired broken links
|
2019-01-03 18:18:03 +01:00 |
|
tangxifan
|
349e634fef
|
Update README.md
|
2018-12-30 14:37:17 -07:00 |
|
tangxifan
|
9f3da4d1a5
|
Update README.md
|
2018-12-30 14:35:07 -07:00 |
|
LNIS-Projects
|
77dd7f3e04
|
correction of the name of the figure
|
2018-12-29 01:45:45 +01:00 |
|
LNIS-Projects
|
0f6ac32f43
|
Further resizing
|
2018-12-29 01:44:24 +01:00 |
|
LNIS-Projects
|
38a3b01520
|
Resize the images
|
2018-12-29 01:42:43 +01:00 |
|
Baudouin Chauviere
|
9ee50de26a
|
Adding information on the layout
|
2018-12-29 01:14:26 +01:00 |
|
Baudouin Chauviere
|
0a5391c14f
|
Addition of some illustrations
|
2018-12-26 18:16:16 +01:00 |
|
LNIS-Projects
|
de7d646fa0
|
Update func_verify.rst
Functional Verification documentation
|
2018-12-26 18:05:24 +01:00 |
|
LNIS-Projects
|
c0626e9a1c
|
Adding the Verification Step from ModelSim
|
2018-12-26 18:00:03 +01:00 |
|
AurelienUoU
|
7ff245448b
|
Add new benchmark and modify go.sh to use it
|
2018-12-26 04:24:26 -07:00 |
|
LNIS-Projects
|
c506e16d33
|
Update command_line_usage.rst
Small fix
|
2018-12-22 14:46:15 +01:00 |
|
LNIS-Projects
|
ba303450e2
|
Update file_organization.rst
|
2018-12-22 14:45:00 +01:00 |
|
LNIS-Projects
|
5fa6c84087
|
New fpga_verilog commands documented
|
2018-12-22 14:39:51 +01:00 |
|
LNIS-Projects
|
41067f6ac1
|
Update .travis.yml
|
2018-12-14 16:13:05 -07:00 |
Robert Weischedel
|
1b6d5b3b5d
|
Update .travis.yml
|
2018-12-14 15:30:25 -07:00 |
|
AurelienUoU
|
2fd05f269e
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-14 14:49:04 -07:00 |
|
AurelienUoU
|
21dc8a006f
|
Change simulator script generation (waves)
|
2018-12-14 14:40:04 -07:00 |
|
LNIS-Projects
|
c0e49b7d4d
|
Update .travis.yml
|
2018-12-14 14:16:04 -07:00 |
|
LNIS-Projects
|
c7915511f7
|
Update .travis.yml
|
2018-12-14 14:12:26 -07:00 |
|
LNIS-Projects
|
74c1067220
|
Update .travis.yml
|
2018-12-14 14:09:09 -07:00 |
|
tangxifan
|
1d426986e5
|
add travis
|
2018-12-14 14:05:31 -07:00 |
|
tangxifan
|
ee6b1d6cd6
|
adapt arch xml and act for demo
|
2018-12-13 22:46:40 -07:00 |
|
tangxifan
|
3d9e913e4e
|
add a benchmark fifo
|
2018-12-12 16:45:33 -07:00 |
|
AurelienUoU
|
cc5a01d476
|
Fix waveform generation + add benchmark and update go.sh
|
2018-12-11 22:21:39 -07:00 |
|
AurelienUoU
|
a70b0ac9ac
|
Correct go.sh
|
2018-12-11 15:51:21 -07:00 |
|
AurelienUoU
|
317c3b59c9
|
Update go.sh and upload pip_add.v
|
2018-12-11 15:47:05 -07:00 |
|
AurelienUoU
|
fb0992bd85
|
Update go.sh and Makefile
|
2018-12-11 15:31:32 -07:00 |
|
AurelienUoU
|
c2c4e78639
|
Add pip_add benchmark
|
2018-12-11 15:29:48 -07:00 |
|
AurelienUoU
|
f5ea3ff233
|
Add an autochecked configuration free testbench
|
2018-12-11 14:44:13 -07:00 |
|
Baudouin Chauviere
|
79f3db9880
|
removed the now useless tutorial part
|
2018-12-10 13:57:01 -07:00 |
|
Baudouin Chauviere
|
ba6ace343b
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-10 13:48:09 -07:00 |
|
LNIS-Projects
|
55459f7906
|
Update index.rst
Reorganization
|
2018-12-10 13:46:38 -07:00 |
|
LNIS-Projects
|
56555fc8a0
|
Update index.rst
Removed abc from the project because included in Yosys
|
2018-12-10 13:46:02 -07:00 |
|
tangxifan
|
8891904e10
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-10 13:30:12 -07:00 |
|
tangxifan
|
72fbd8d6a8
|
update blif reader to identify clock signals
|
2018-12-10 13:28:44 -07:00 |
|
LNIS-Projects
|
7bcc61b0f2
|
Update .gitmodules
Unused submodule blocking the compilation of the documentation
|
2018-12-10 12:07:05 -07:00 |
|
Baudouin Chauviere
|
1472e7aa62
|
Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA
|
2018-12-10 10:25:25 -07:00 |