tangxifan
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852b01aaff
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[test] rework
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2024-05-20 17:20:04 -07:00 |
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tangxifan
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a9a5fbee34
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[test] add fully connected feedback connections to directlist
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2024-05-20 17:02:20 -07:00 |
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tangxifan
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6146d0be9f
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[arch] Move clb I to right side as left side is not supported yet
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2024-05-20 13:43:04 -07:00 |
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tangxifan
|
65dd342c60
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[arch] typo
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2024-05-20 12:11:22 -07:00 |
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tangxifan
|
c795dd2f1a
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[arch] adding a new arch where feedback loops are modelled by direct connections
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2024-05-20 12:00:39 -07:00 |
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tangxifan
|
3615bdceeb
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[test] avoid no-fanin errors for hetero arch
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2024-05-06 15:32:27 -07:00 |
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tangxifan
|
dff03e7993
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[test] enable missing options in the arch used by benchmark sweeping tests
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2023-11-14 09:45:02 -08:00 |
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tangxifan
|
0b473e3454
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[test] fixed the bug in single-mode lut testcase
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2023-11-14 09:35:26 -08:00 |
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tangxifan
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d108284105
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[test] update arch to keep golden outputs
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2023-11-14 09:31:07 -08:00 |
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tangxifan
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913434b70d
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[test] fixed the bug that golden netlists are modified
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2023-11-14 09:28:57 -08:00 |
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tangxifan
|
59d086a27f
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[test] try to keep the golden inputs
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2023-11-14 09:25:45 -08:00 |
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tangxifan
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1b8748abb4
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[core] update vtr
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2023-11-13 14:21:34 -08:00 |
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tangxifan
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d78f18d235
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[test] add new testcase
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2023-11-13 14:11:34 -08:00 |
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tangxifan
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56cedf6c8b
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[test] added a new test case to validate the support on different wire segment distribution on X and Y
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2023-08-22 11:20:14 -07:00 |
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tangxifan
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1b132fd667
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[test] add a new testcase to validate the support on different routing channel width on X and Y
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2023-08-22 11:06:12 -07:00 |
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tangxifan
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e4c5265b68
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[test] arch syntax
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2023-08-18 21:40:56 -07:00 |
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tangxifan
|
5ac8919ce0
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[test] add a new testcase to validate subtile with tile annotations
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2023-08-18 21:37:15 -07:00 |
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tangxifan
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f69520d0c3
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[arch] format
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2023-08-18 11:15:25 -07:00 |
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tangxifan
|
170a49c34f
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[test] fix a bug in arch file
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2023-08-18 11:15:05 -07:00 |
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tangxifan
|
e82e4f487e
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[test] add a new test to validate io subtile support
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2023-08-18 11:13:34 -07:00 |
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tangxifan
|
4afd48d930
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[test] format
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2023-08-17 15:33:09 -07:00 |
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tangxifan
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463897f78e
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[test] fixed a bug in arch
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2023-08-17 15:28:59 -07:00 |
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tangxifan
|
3ac3eb4624
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[test] adding more flavor to the L shape
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2023-08-17 15:08:27 -07:00 |
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tangxifan
|
253d5fa26c
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[core] a new test to validate the L shape in homo geneous fpga
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2023-08-11 13:05:46 -07:00 |
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tangxifan
|
dc0eec8b81
|
[test] added a new test to validate L shapre
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2023-08-11 12:49:38 -07:00 |
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tangxifan
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5685fbd5e8
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[test] adding a new test case to validate the tile modules on 4x4 fabric
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2023-07-26 22:17:39 -07:00 |
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tangxifan
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f89b7a82cf
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[arch] fixed a bug where the array size mismatch the layout name
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2023-05-03 22:23:20 +08:00 |
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tangxifan
|
a3f2ae3c33
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[arch] format
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2023-05-03 15:23:47 +08:00 |
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tangxifan
|
68f2d9fe5e
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[arch] add new example arch using subtile in I/O blocks; Updated documentation
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2023-05-03 15:16:39 +08:00 |
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tangxifan
|
02b02d18a5
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[test] fixed a bug in clock arch
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2023-04-20 11:35:36 +08:00 |
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tangxifan
|
b242fd97d6
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[test] adding new arch and testcase for 2-clock network
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2023-04-20 11:31:49 +08:00 |
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tangxifan
|
571a012724
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[test] xml format
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2023-03-07 18:47:55 -08:00 |
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tangxifan
|
7e3b656c51
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[test] fixed a bug in arch
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2023-03-06 23:06:32 -08:00 |
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tangxifan
|
b9f7c72a96
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[test] fixed some bugs in arch
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2023-03-02 18:16:59 -08:00 |
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tangxifan
|
5917446fbe
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[arch] code format
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2023-02-28 22:01:49 -08:00 |
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tangxifan
|
780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |
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tangxifan
|
d1e951e52e
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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tangxifan
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1d8c1a6803
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[arch] adding a new arch to validate fracturable dsp
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2023-01-24 15:17:50 -08:00 |
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tangxifan
|
acc905fa11
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[arch] add support to route reset to LUTs
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2023-01-18 18:22:37 -08:00 |
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tangxifan
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c9e00b7abc
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[arch] add a new example arch that supports local reset
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2023-01-18 18:05:52 -08:00 |
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tangxifan
|
297092f1fe
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[arch] now use a local clock as an input of a CLB
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2023-01-14 22:12:00 -08:00 |
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tangxifan
|
9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
|
9e462d96e0
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[arch] now use a dedicated input for locally generated clock signals
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2023-01-13 20:46:04 -08:00 |
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tangxifan
|
1fb39f803b
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[doc] updated vpr arch naming rules
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2023-01-13 19:52:58 -08:00 |
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tangxifan
|
a06ee30ca0
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[arch] added a new vpr arch where clock can be generated by internal logics
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2023-01-13 19:35:00 -08:00 |
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tangxifan
|
32f48f16c7
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[arch] fixed a few bugs
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2022-10-13 11:54:58 -07:00 |
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tangxifan
|
7f67794787
|
[arch]add new arch to test
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2022-10-13 10:54:40 -07:00 |
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tangxifan
|
85089cbc88
|
[arch] apply xml format for all the architecture files
|
2022-10-07 10:31:51 -07:00 |
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tangxifan
|
ab53f88c2b
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[test] now use a fixed device layout for the single-mode LUT design testcase
|
2022-10-04 10:05:22 -07:00 |
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tangxifan
|
0565ca7aca
|
[script] add missing files
|
2022-09-29 16:14:38 -07:00 |