tangxifan
|
a9e6b7c12e
|
[FPGA-Bitstream] Remove version numbers when ``--no_time_stamp`` is enabled
|
2022-01-25 20:33:49 -08:00 |
|
tangxifan
|
fedb1bd2e3
|
[Test] Add new testcases to validate correctness of the testbenches/Verilog netlists without time stamp
|
2022-01-25 16:41:36 -08:00 |
|
tangxifan
|
6e778a74ee
|
[Test] Add golden reference for files outputted without time stamp
|
2022-01-25 16:24:25 -08:00 |
|
tangxifan
|
2bee59c6ca
|
[Test] Add the testcase to validate ``--no_time_stamp``
|
2022-01-25 16:21:15 -08:00 |
|
tangxifan
|
dd803dd1de
|
[Test] Remove unused tests
|
2022-01-25 16:16:58 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
397f2e71f1
|
Added 'basic_tests/explicit_multi_verilog_files' task and deployed it to CI. Reverted previous commit chenges in 'benchmark_sweep/iwls2005' task.
|
2022-01-19 20:43:26 +05:00 |
|
Aram Kostanyan
|
bd158311c5
|
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
|
2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
6a4cc340a3
|
Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
|
2022-01-17 13:21:29 +05:00 |
Awais Abbas
|
598c5e6b75
|
Test case for yosys-only flow added
|
2022-01-14 15:37:47 +05:00 |
|
tangxifan
|
824a03bdca
|
[Flow] Patch new test case
|
2022-01-02 20:20:36 -08:00 |
|
tangxifan
|
55da99f4ca
|
[Flow] Add a new test case to validate DSP with registers
|
2022-01-02 20:08:23 -08:00 |
nadeemyaseen-rs
|
06fb4b0ece
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-25 00:00:22 +05:00 |
coolbreeze413
|
31379062e3
|
remove minor comments
|
2021-11-18 18:40:15 +05:30 |
|
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
coolbreeze413
|
91094305bd
|
enable all tests except 15 and 19
|
2021-11-17 20:56:12 +05:30 |
|
coolbreeze413
|
840fa399c6
|
enable single counter test (fails, needs debug)
|
2021-11-09 21:36:33 +05:30 |
|
Aram Kostanyan
|
b332a5a1b4
|
Added 'basic_tests/verific_test' test-case.
|
2021-11-01 18:20:57 +05:00 |
|
tangxifan
|
ff264c00a2
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-31 11:51:34 -07:00 |
|
tangxifan
|
7f999d03c6
|
[Test] update golden results for the vtr benchmarks due to Yosys v0.10 uprade
|
2021-10-30 18:05:39 -07:00 |
|
tangxifan
|
370e3fef83
|
[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks
|
2021-10-30 18:03:59 -07:00 |
|
tangxifan
|
c8e9dfbeda
|
[Test] bug fix
|
2021-10-30 16:50:57 -07:00 |
|
tangxifan
|
a4cfc84930
|
[Test] Bug fix
|
2021-10-30 16:00:47 -07:00 |
|
tangxifan
|
335347a74f
|
[Test] Bug fix
|
2021-10-30 15:48:25 -07:00 |
|
tangxifan
|
be47e78289
|
[Arch] Change arch for Sapone test
|
2021-10-30 15:23:19 -07:00 |
|
tangxifan
|
ad5cce0ae8
|
[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
|
2021-10-30 15:11:07 -07:00 |
|
tangxifan
|
40d11a45d9
|
[Test] Disable ACE2 in implicit verilog test cases due to Yosys upgrade
|
2021-10-30 14:49:56 -07:00 |
|
tangxifan
|
16de60e943
|
[Test] Turn off ACE2 run in bitstream generation only flows
|
2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
b2c4e3314e
|
[Test] Bug fix in test cases
|
2021-10-11 10:28:09 -07:00 |
|
tangxifan
|
8566e2a0cd
|
[Test] Renaming test case to follow naming convention as other fabric key test cases
|
2021-10-11 09:56:23 -07:00 |
|
tangxifan
|
b8b02d37d5
|
[Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file
|
2021-10-11 09:53:23 -07:00 |
|
tangxifan
|
6122863548
|
[Test] Add a test case to validate the multi-shift-register-chain QL memory bank
|
2021-10-09 20:44:28 -07:00 |
|
tangxifan
|
a1eaacf5a8
|
[Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency
|
2021-10-06 12:12:15 -07:00 |
|
tangxifan
|
b98a8ec718
|
[Test] Added the dedicated test case for fixed shift register clock frequency
|
2021-10-06 12:09:26 -07:00 |
|
tangxifan
|
189ade6c1e
|
[Test] Bug fix
|
2021-10-05 19:17:34 -07:00 |
|
tangxifan
|
f74ea5d39a
|
[Test] Use the new openfpga shell script in don't care bit tests
|
2021-10-05 19:14:44 -07:00 |
|
tangxifan
|
50604e4589
|
[Test] move test cases
|
2021-10-05 19:02:43 -07:00 |
|
tangxifan
|
fed6c133b1
|
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
|
2021-10-05 18:59:33 -07:00 |
|
tangxifan
|
b21f212031
|
[Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key
|
2021-10-05 11:39:53 -07:00 |
|
tangxifan
|
52569f808e
|
[Test] Added a test case for QuickLogic memory bank using shift registers in multiple region
|
2021-10-05 10:57:33 -07:00 |
|
tangxifan
|
fa1908511d
|
[Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control
|
2021-10-04 16:36:20 -07:00 |
|
tangxifan
|
dda147e234
|
[Flow] Add an example simulation setting file for defining programming shift register clocks
|
2021-10-01 11:04:23 -07:00 |
|
tangxifan
|
89a97d83bd
|
[Test] Added a new test case for the shift register banks in QuickLogic memory banks
|
2021-09-29 16:28:06 -07:00 |
|
tangxifan
|
4400dae108
|
[Test] Bug fix in the wrong arch name
|
2021-09-28 11:40:25 -07:00 |
|
tangxifan
|
dae3554fd4
|
[Test] Add a new test case for QL memory bank with flatten BL/WL buses using WLR signals
|
2021-09-28 11:27:49 -07:00 |
|
tangxifan
|
655b195d8b
|
[Test] Added a test case to validate the correctness of QL memory bank where BL/WL are flatten on the top level
|
2021-09-22 15:56:44 -07:00 |
|
tangxifan
|
b0aaab9c03
|
[Test] Bug fix due to mismatches in device layout between fabric key and VPR settings
|
2021-09-22 11:32:13 -07:00 |
|
tangxifan
|
abfa380333
|
[Test] Added a test case to validate the fabric key of 2-region QL memory bank
|
2021-09-22 11:27:09 -07:00 |
|
tangxifan
|
51fc222d61
|
[Test] Added a new test case for multi-region QL memory bank
|
2021-09-22 10:01:33 -07:00 |
|
tangxifan
|
1412121541
|
[Test] Added a new test to validate the fabric key parser for QL memory bank
|
2021-09-21 16:20:24 -07:00 |
|
tangxifan
|
dc2d1d1c3c
|
[Test] Add a new test case to validate the correctness of fabric key file for ql memory bank
|
2021-09-21 15:42:20 -07:00 |
|
tangxifan
|
60fc3ab36c
|
[Test] Added a new test case for the WLR memory bank
|
2021-09-20 11:20:36 -07:00 |
|
tangxifan
|
b82cfdf555
|
[Test] Add the QL memory bank test to regression test cases
|
2021-09-09 09:29:21 -07:00 |
|
tangxifan
|
6adf439081
|
Merge remote-tracking branch 'upstream/master'
|
2021-09-01 14:19:00 -07:00 |
|
tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |
|
tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
|
2021-07-02 17:29:13 -06:00 |
|
tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
|
tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
|
2021-07-02 14:04:42 -06:00 |
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
ANDREW HARRIS POND
|
006b54c4bc
|
ready for merge
|
2021-07-01 15:35:39 -06:00 |
|
ANDREW HARRIS POND
|
8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
|
2021-07-01 15:29:39 -06:00 |
|
ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
|
tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
|
2021-07-01 14:43:26 -06:00 |
|
ANDREW HARRIS POND
|
db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
komaljaved-rs
|
be14e4f448
|
added design_variables.yml
|
2021-07-01 16:31:42 +05:00 |
|
komaljaved-rs
|
6559f71082
|
added ci_scripts
|
2021-07-01 15:07:37 +05:00 |
|
tangxifan
|
83d177b13b
|
[Test] Deploy the newly added adder benchmarks to tests
|
2021-06-30 15:14:24 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
30c2f597f2
|
[Test] Added two cases to validate testbench generation without self checking
|
2021-06-29 16:06:15 -06:00 |
|
tangxifan
|
6f0600e17f
|
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
|
2021-06-27 19:56:01 -06:00 |
|
tangxifan
|
477cba1c7e
|
Merge branch 'master' into verilog_testbench
|
2021-06-23 09:18:18 -06:00 |
|
tangxifan
|
f06017581c
|
[Test] Bug fix in counter micro benchmark tests
|
2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
760570d883
|
[Test] Update counter test case for cover most counter HDL design
|
2021-06-21 18:13:18 -06:00 |
|
tangxifan
|
9c24a739be
|
[Test] Added a MAC benchmark sweeping test
|
2021-06-21 17:40:53 -06:00 |
Andrew Pond
|
3cfc42cdf9
|
added testbench CI
|
2021-06-15 14:16:31 -06:00 |
|
tangxifan
|
eed30605d7
|
[Test] patch test case
|
2021-06-09 15:20:55 -06:00 |
|
tangxifan
|
52c0ed571b
|
[Test] Patch test case to use proper template
|
2021-06-09 14:27:02 -06:00 |
|
tangxifan
|
c62666e7c3
|
[Test] Use proper template for some failing tests
|
2021-06-09 14:24:34 -06:00 |
|
tangxifan
|
462326aaa5
|
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
|
2021-06-07 21:50:00 -06:00 |
|
tangxifan
|
5ecd975ec7
|
[Test] Bug fix
|
2021-06-07 19:20:10 -06:00 |
|
tangxifan
|
9556f994b4
|
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
|
2021-06-07 17:49:40 -06:00 |
|
tangxifan
|
a67196178e
|
[Test] Now use 'write_full_testbench' in configuration frame test cases
|
2021-06-07 13:58:15 -06:00 |
|
tangxifan
|
27fa15603a
|
[Tool] Patch test case due to changes in the template script
|
2021-06-04 18:17:47 -06:00 |
|
tangxifan
|
5f96d440ec
|
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
|
2021-06-04 11:48:05 -06:00 |
|
tangxifan
|
ec203d3a5c
|
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
|
2021-06-04 11:35:23 -06:00 |
|
tangxifan
|
2068291de0
|
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
|
2021-06-04 11:32:49 -06:00 |
|
tangxifan
|
aa4e1f5f9a
|
[Test] Update test case which uses write_full_testbench openfpga shell script
|
2021-06-04 11:29:43 -06:00 |
|
tangxifan
|
ebe30fc070
|
[Test] Deploy write full testbench to multi-head configuration chain test case
|
2021-06-03 17:08:33 -06:00 |
|
tangxifan
|
1e9f6eb439
|
[Test] update configuration chain test to use new testbench
|
2021-06-03 15:53:27 -06:00 |
|
tangxifan
|
2baf3ddd2f
|
[Test] Add test cases for 'report_bitstream_distribution' command
|
2021-05-07 12:06:24 -06:00 |
|
tangxifan
|
f1658cb735
|
[Test] Deploy blinking to test cases
|
2021-05-06 15:17:45 -06:00 |
|
tangxifan
|
a5e40fbb21
|
Merge branch 'master' into micro_benchmarks
|
2021-04-28 14:27:58 -06:00 |
|
tangxifan
|
b72d4bd807
|
[Test] Update test case for 1kbit DPRAM architectures
|
2021-04-28 11:28:53 -06:00 |
|
tangxifan
|
5c729657ef
|
[Test] Bug fix in test case for DPRAM whose width = 2
|
2021-04-28 10:31:22 -06:00 |