tangxifan
|
8aa665b3b2
|
bug fix in the Verilog codes for frame decoders
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
1e73fd6def
|
create configuration frame example script
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
8298bbff78
|
bug fixed in the fabric bitstream for frame-based configurable memories.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
bf9f62f0f7
|
keep bug fixing for frame-based configuration protocol.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3fa3b17061
|
start testing the frame-based configuration protocol. To distinguish, rename xml to identify between configuration chain and frame-based. This should not impact the pre-config testbenches.
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
ece651ade2
|
bug fixed in the configuration chian errrors
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
cff5b5cfc1
|
break the configuration testbench. This commit is to spot which modification leads to the problem
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
85921dcc05
|
add fabric bitstream builder for frame-based configuration protocol
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
4a0e1cd908
|
add fabric bitstream data structure and deploy it to Verilog testbench generation
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
8c14cced84
|
start improve fabric bitstream database to support frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
5c5a044c68
|
add architecture decoder (for frame-based config memory) to Verilog writer
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
c696e3d20f
|
refine frame-based memory addition to compact the area
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
ed2325ec9e
|
add frame decoder build-up to top-level module
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
290dd1a8a6
|
add frame decoder builder to all the module graph builder except the top-level
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
8864920460
|
add frame-based memory module builder
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
3a26bb5eef
|
add advanced check in configurable memories
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
62c506182c
|
start developing frame-based configuration protocol
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
1150b903a5
|
add quick start tutorial for architecture modeling
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
339bf87c43
|
add missing file
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
aa77ee9af6
|
add tutorial for full testbench run
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
35536ee594
|
renaming design flows in documentation
|
2020-06-11 19:31:09 -06:00 |
|
tangxifan
|
011ce5cdf6
|
minor fix on the documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f079c61bd3
|
re organize tutorials
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
dcce782a46
|
update documentation about Verilog testbenches
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c5a3e44e61
|
Update Verilog fabric netlist documentation
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
cae7fe0fed
|
minor fix on the manual subtree
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
c27d77a418
|
clean-up documentation for a shallow hierarchy
|
2020-06-11 19:31:08 -06:00 |
|
tangxifan
|
f6895fcc14
|
update documentation for new options of Verilog testbench writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
bba476fef4
|
add explicit port mapping support to Verilog testbench generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
6f133bd009
|
bug fix in packable mode support
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
e089b0ef22
|
use constant string for inverted port naming
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
c2a81c76e1
|
update doc for new options
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
8915d10d27
|
add verbose output option to configure port disable timing writer
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
6177921d4c
|
bug fixed in configure port disable timing. Now we disable the right ports of LUTs
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
f52b5d5b4c
|
use error code in read_arch command
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
e9ceedb01b
|
use constant openfpga context in SDC generator
|
2020-06-11 19:31:07 -06:00 |
|
tangxifan
|
910be3cadb
|
massively deploy disable_timing for configure ports in CI
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
067d09f954
|
bug fix for configure port disable_timing writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
f4dd882f0f
|
documentation updated for new command
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
13f591cacf
|
add new command to disable timing for configure ports of programmable modules
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
ae9f1fbd90
|
critical bug fixed in the disable MUX output
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
99751b84f5
|
bug fix in configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
df9cf32b49
|
update documenation for configuration chain writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
a41c8dbcb3
|
change to use default sphinx build version
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
02e86c565a
|
bug fix in configuration chain SDC writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
fc2b09514e
|
add configuration chain write to regression tests
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
4c0953415b
|
add configuration chain sdc writer
|
2020-06-11 19:31:06 -06:00 |
|
tangxifan
|
dad99d13a2
|
bug fixed in SDC timing writer for primitive pb_type
|
2020-06-11 19:31:06 -06:00 |