tangxifan
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74e94b855e
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[core] fixed a bug where gsb OPIN name does not match the switch block module
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2024-05-29 10:27:10 -07:00 |
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tangxifan
|
ca6e2f9831
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[core] code format
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2024-05-20 13:41:35 -07:00 |
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tangxifan
|
4a791249bf
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[core] fixed a bug on requirement wire model for direction connection which is part of a cb
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2024-05-20 12:52:07 -07:00 |
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tangxifan
|
918bf79ca3
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[core] update vtr and developing caches for OPIN lists just for connection blocks
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2024-05-19 14:10:00 -07:00 |
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tangxifan
|
717906ea17
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[core] code format
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2023-08-25 15:13:39 -07:00 |
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tangxifan
|
89b392a51f
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[core] adapt changes in is_sb_exist()
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2023-08-25 15:13:00 -07:00 |
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tangxifan
|
55e5f738ce
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[core] code format
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2023-08-25 11:58:15 -07:00 |
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tangxifan
|
92f92658c9
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[core] remove useless errors
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2023-08-25 11:53:49 -07:00 |
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tangxifan
|
399f087c50
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[core] code format
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2023-08-17 13:54:31 -07:00 |
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tangxifan
|
414f7379c6
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[core] fixed some bugs in debugging messages
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2023-08-17 13:52:21 -07:00 |
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tangxifan
|
788e3c17a9
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[core] format
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2023-08-08 23:02:20 -07:00 |
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tangxifan
|
1c8c4fedbb
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[core] fix memory leak
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2023-08-08 23:01:52 -07:00 |
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tangxifan
|
ff6fa1e90c
|
[core] fix memory leak
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2023-08-08 22:41:43 -07:00 |
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tangxifan
|
94d80a9b7c
|
[core] code format
|
2023-08-08 16:28:56 -07:00 |
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tangxifan
|
867da98d3f
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[core] update to use latest api from vpr upstream
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2023-08-08 16:28:19 -07:00 |
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tangxifan
|
beaa687a20
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[core] fixed bugs on supporting heterogeneous blocks in tile modules
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2023-07-27 20:29:18 -07:00 |
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tangxifan
|
c2066cc63c
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[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules
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2023-07-27 13:33:23 -07:00 |
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tangxifan
|
156cb800aa
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[core] fixed a critical bug which causes wrong connections in tile modules
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2023-07-27 12:22:16 -07:00 |
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tangxifan
|
97219fd825
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[core] add more verbose to help debug failed test cases
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2023-07-26 23:26:11 -07:00 |
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tangxifan
|
f5e8f175fb
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[core] fixed a bug which causes flow failures when group_tile is not enabled
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2023-07-25 21:27:58 -07:00 |
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tangxifan
|
da36b735c6
|
[core] syntax
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2023-07-24 12:13:45 -07:00 |
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tangxifan
|
93c5a68592
|
[core] developing top-level nets for tiles
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2023-07-21 23:21:53 -07:00 |
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tangxifan
|
6b92299e39
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[core] start working on the net build-up for tile instances under the top-level module
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2023-07-20 17:38:13 -07:00 |
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tangxifan
|
a06b9a0f48
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[core] now start to develop the tile instances under the top module
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2023-07-19 22:22:07 -07:00 |
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tangxifan
|
0d03d7b483
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[core] now fabric tile cache both grid and gsb coord for pb
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2023-07-19 17:20:53 -07:00 |
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tangxifan
|
778d03610c
|
[core] debugging
|
2023-07-19 15:27:05 -07:00 |
|
tangxifan
|
001b3b3f8b
|
[core] debugging
|
2023-07-19 14:38:07 -07:00 |
|
tangxifan
|
d03fa92ddf
|
[core] debugging
|
2023-07-19 12:49:35 -07:00 |
|
tangxifan
|
48e207d3e4
|
[core] debugging
|
2023-07-19 12:22:57 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
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tangxifan
|
5ae146bd86
|
[core] finish up tile module builder
|
2023-07-18 21:17:40 -07:00 |
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tangxifan
|
403ed4ea60
|
[core] still developing tile module port and net builder
|
2023-07-18 16:03:47 -07:00 |
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tangxifan
|
aabcc25567
|
[core] developing tile module port and net builder
|
2023-07-17 23:06:55 -07:00 |
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tangxifan
|
ba4b7e3522
|
[core] developing tile module builder
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2023-07-16 15:18:09 -07:00 |
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tangxifan
|
98c598cec2
|
[core] unique tile identifier done
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2023-07-15 22:54:33 -07:00 |
|
tangxifan
|
ea8d128789
|
[core] syntax
|
2023-07-15 20:29:21 -07:00 |
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tangxifan
|
c2ef5ca408
|
[core] developing top-left style tile info
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2023-07-14 22:48:44 -07:00 |
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tangxifan
|
327f7f4dab
|
[core] now adapt to latest API of DeviceGrid
|
2023-06-07 18:54:48 -07:00 |
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tangxifan
|
aeeee6d8bd
|
[core] code format
|
2023-04-20 15:07:54 +08:00 |
|
tangxifan
|
40598d25a3
|
[core] fixed a bug which causes multi-clock programmable network failed in routing
|
2023-04-20 15:05:45 +08:00 |
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tangxifan
|
928c7d5736
|
Merge branch 'master' into xt_clk_arch
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2023-04-19 22:17:33 +08:00 |
|
tangxifan
|
cb4512b925
|
[core] code format
|
2023-04-19 11:10:42 +08:00 |
|
tangxifan
|
a84cc52d7c
|
[core] fixed a few bugs due to the changes in vtr regarding flat router
|
2023-04-19 11:08:18 +08:00 |
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tangxifan
|
11f09db556
|
[core] fixed a bug where clock tracks do not pass through at higher level
|
2023-03-07 15:05:56 -08:00 |
|
tangxifan
|
50e201feeb
|
[core] now clock routing for programmable clock network works for 1 clock design
|
2023-03-07 13:13:25 -08:00 |
|
tangxifan
|
2ff3ad61ce
|
[core] format
|
2023-03-06 21:57:44 -08:00 |
|
tangxifan
|
45107bf14f
|
[core] debugging
|
2023-03-06 21:48:19 -08:00 |
|
tangxifan
|
c23b8e579d
|
[core] fixed a bug
|
2023-03-06 17:10:14 -08:00 |
|
tangxifan
|
9823983b30
|
[core] debuggign
|
2023-03-06 15:57:37 -08:00 |
|
tangxifan
|
1633279c65
|
[core] fixed a bug in building edges for nodes
|
2023-03-06 14:50:28 -08:00 |