tangxifan
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c6ac02d210
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[FPGA-SPICE] Add VDD/VSS ports to SPICE subckt instanciation
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2020-09-20 15:21:33 -06:00 |
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tangxifan
|
544c44fe46
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[FPGA-SPICE] Add VDD and VSS port to module definition
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2020-09-20 14:58:15 -06:00 |
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tangxifan
|
460fef5807
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[FPGA-Verilog] Rename files and functions to distinguish from FPGA-SPICE files and functions
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2020-09-20 12:58:55 -06:00 |
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tangxifan
|
222bc86cbf
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[FPGA-SPICE] Add auxiliary SPICE netlist writer
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2020-09-20 12:53:28 -06:00 |
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tangxifan
|
06c0073a3e
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[FPGA-SPICE] Add SPICE writer for fpga top module
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2020-09-20 12:43:48 -06:00 |
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tangxifan
|
1dfb3e06cc
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[FPGA-SPICE] add SPICE writer for logic blocks
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2020-09-20 12:38:24 -06:00 |
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tangxifan
|
5e78e91fdf
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[FPGA-SPICE] Add SPICE writer for routing blocks
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2020-09-20 12:27:48 -06:00 |
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tangxifan
|
0f25b52907
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[FPGA-Verilog] code format fix
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2020-09-20 12:18:22 -06:00 |
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tangxifan
|
2fae311c8e
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[FPGA-SPICE] Add SPICE writer for memories
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2020-09-20 12:14:34 -06:00 |
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tangxifan
|
f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
|
6801d260e9
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[FPGA-SPICE] Add SPICE writer for LUT
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2020-09-20 11:58:11 -06:00 |
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tangxifan
|
0f9fce92b2
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[FPGA-SPICE] Add SPICE writer for routing multiplexers
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2020-09-20 11:49:02 -06:00 |
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tangxifan
|
c7e3d97d1b
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[FPGA-SPICE] Add supply voltage generator
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2020-09-20 11:19:06 -06:00 |
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tangxifan
|
15df9b3893
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[FPGA-SPICE] Add SPICE subcircuit writer
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2020-09-19 23:01:44 -06:00 |
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tangxifan
|
82e137cbe4
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[FPGA-SPICE] Add wire module SPICE writer
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2020-09-19 19:31:16 -06:00 |
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tangxifan
|
1b2762386c
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[FPGA-SPICE] Bug fix for essential gate netlist writing
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2020-09-19 16:52:30 -06:00 |
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tangxifan
|
26a0a769ea
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[FPGA-SPICE] Split essential gate SPICE netlists into separated files
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2020-09-19 16:45:26 -06:00 |
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tangxifan
|
e102e30d19
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[FPGA-SPICE] Add support for AND/OR logic gate
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2020-09-19 16:20:21 -06:00 |
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tangxifan
|
482d90018f
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[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
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2020-09-19 15:33:28 -06:00 |
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tangxifan
|
3262ceb276
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[FPGA-SPICE] Bug fix for pass gate transistor sizing
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2020-09-19 15:24:40 -06:00 |
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tangxifan
|
aa078f079c
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[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
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2020-09-19 15:20:19 -06:00 |
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tangxifan
|
f5dadca884
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[FPGA-SPICE] Optimize the print-out of SPICE ports
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2020-09-19 15:07:48 -06:00 |
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tangxifan
|
51d423e4db
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[FPGA-SPICE] Add pass-gate SPICE netlist writer
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2020-09-19 14:59:00 -06:00 |
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tangxifan
|
9cfb2f52ef
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[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
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2020-09-16 19:26:46 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
04070fd4ca
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
|
2020-09-02 22:16:10 -06:00 |
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tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
|
f631245b2b
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bug fix and enriched debugging info print out
|
2020-08-19 13:41:04 -06:00 |
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tangxifan
|
79b6ff3cb0
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relax checking for device annotation as we support multi-port during physical mode pin mapping
|
2020-08-19 12:44:51 -06:00 |
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tangxifan
|
2712c354a9
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now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
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tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
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tangxifan
|
9a7364c6e6
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bug fix in fabric bitstream XML syntax
|
2020-07-27 19:22:36 -06:00 |
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tangxifan
|
35af0dd676
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streamline fabric bitstream file format
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2020-07-27 16:34:43 -06:00 |
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tangxifan
|
8dd26094b8
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add root node to fabric bitstream XML file format
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2020-07-27 15:31:08 -06:00 |
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tangxifan
|
6592db3dfe
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bug fix in calling the wrong function of write_fabric_bitstream
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2020-07-27 14:32:58 -06:00 |
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tangxifan
|
d68e77f322
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Split the writer of build_fabric_bitstream to a separated command so that users will output multiple files in different formats
|
2020-07-27 14:16:33 -06:00 |
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tangxifan
|
e09eddab43
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add width syntex to the fabric bitstream file format
|
2020-07-27 13:54:23 -06:00 |
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tangxifan
|
80e982fb39
|
minor file format fix in fabric bitstream XML
|
2020-07-26 21:35:48 -06:00 |
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tangxifan
|
b3ad04fd1e
|
minor file format fix in fabric bitstream XML
|
2020-07-26 21:33:47 -06:00 |
|
tangxifan
|
861e346830
|
minor bug fix in fabric bitstream XML writer
|
2020-07-26 21:31:08 -06:00 |
|
tangxifan
|
5fb7d9fbdb
|
bug fix in fabric bitstream file format writer
|
2020-07-26 21:28:45 -06:00 |
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tangxifan
|
92d2d2d849
|
add fabric bitstream XML writer
|
2020-07-26 21:00:57 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
fd3e947c6d
|
update FPGA_SPICE to support max width for transistors and multi-bin
|
2020-07-24 17:52:31 -06:00 |
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tangxifan
|
73e2b857a3
|
add buffer support to FPGA-SPICE
|
2020-07-24 15:54:18 -06:00 |
|
tangxifan
|
2603836111
|
split logical tile netlists to keep good Verilog hierarchy
|
2020-07-24 12:53:21 -06:00 |
|
tangxifan
|
be5966475e
|
formulate file name, module name and instance name to be consistent
|
2020-07-24 12:23:27 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
a4a38f8156
|
support multi-bit power gate ports in FPGA-SPICE
|
2020-07-22 20:04:39 -06:00 |
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tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |