tangxifan
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c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
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tangxifan
|
9dc9c2c9f7
|
add build top module connection functions
|
2020-02-14 10:45:24 -07:00 |
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tangxifan
|
36179b6ced
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start moving top-module builder. Now adapt the utils
|
2020-02-14 10:00:24 -07:00 |
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tangxifan
|
afe8278670
|
put routing module builder online
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2020-02-13 17:35:29 -07:00 |
|
tangxifan
|
cf440f92d3
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put routing module builder util function online
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2020-02-13 16:05:23 -07:00 |
|
tangxifan
|
89086ed080
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add verbose output to build grid module
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2020-02-13 15:38:26 -07:00 |
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tangxifan
|
072965cd64
|
make grid module builder online; basic support on physical tiles
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2020-02-13 15:27:16 -07:00 |
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tangxifan
|
59d579425e
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add utils for duplicate pins in grid module builder
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2020-02-12 20:48:07 -07:00 |
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tangxifan
|
895d5b5a0a
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add utils for grid module builder
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2020-02-12 20:25:05 -07:00 |
|
tangxifan
|
002c2795fe
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add memory module builder
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2020-02-12 20:06:38 -07:00 |
|
tangxifan
|
8e381f0581
|
add wire module builder
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2020-02-12 19:57:15 -07:00 |
|
tangxifan
|
e842150cc5
|
add lut module builder
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2020-02-12 19:52:41 -07:00 |
|
tangxifan
|
fddd3c9463
|
add mux module builder
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2020-02-12 19:45:14 -07:00 |
|
tangxifan
|
ea7d879b4f
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add decoder module builder
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2020-02-12 18:28:50 -07:00 |
|
tangxifan
|
f11832b8cf
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start integrating module graph builder
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2020-02-12 17:53:23 -07:00 |
|
tangxifan
|
13fadd0f91
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move compact routing hierarchy to build_fabric command
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2020-02-12 15:49:47 -07:00 |
|
tangxifan
|
c78d3e9af1
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add mux library builder
|
2020-02-12 14:58:23 -07:00 |
|
tangxifan
|
ce63b1cc62
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add circuit model binding for direct connections and enhance model type checking
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2020-02-12 11:40:20 -07:00 |
|
tangxifan
|
4a05cec037
|
add rr_segment binding to circuit model
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2020-02-12 11:21:40 -07:00 |
|
tangxifan
|
a736e09c29
|
add rr_switch binding in link openfpga arch command
|
2020-02-12 10:52:20 -07:00 |
|
tangxifan
|
feccbc5780
|
add more methods to link routing to circuit models in device annotation
|
2020-02-12 10:08:54 -07:00 |
|
tangxifan
|
a31d6c6d1e
|
rename pb_type annotation to device annotation
|
2020-02-12 09:52:18 -07:00 |
|
tangxifan
|
4367dba9b7
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
tangxifan
|
175bef014a
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
tangxifan
|
1372f748f1
|
put GSB builder online
|
2020-02-11 16:37:14 -07:00 |
|
tangxifan
|
85f3826939
|
put device rr_gsb online. Ready to plug-in
|
2020-02-09 14:58:23 -07:00 |
|
tangxifan
|
230c7b709a
|
put rr_gsb data structure online
|
2020-02-09 00:20:44 -07:00 |
|
tangxifan
|
0b6b3bc029
|
start adapting rr_gsb related data structure
|
2020-02-07 11:32:33 -07:00 |
|
tangxifan
|
3d7eff64b9
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |
|
tangxifan
|
ed9e038845
|
add functionality of LUT truth table fix-up
|
2020-02-06 17:14:29 -07:00 |
|
tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
|
2020-02-06 12:54:55 -07:00 |
|
tangxifan
|
cccbb9fd49
|
add missing files
|
2020-02-05 22:12:44 -07:00 |
|
tangxifan
|
dad204674b
|
done an initial version of clustering net fix-up based on routing results. Debugging on the way
|
2020-02-05 21:50:52 -07:00 |
|
tangxifan
|
5006a4395d
|
bring RRGraph object and writer online
|
2020-01-31 16:39:40 -07:00 |
|
tangxifan
|
75c3507acf
|
add verbose output option for openfpga linking architecture
|
2020-01-31 11:36:58 -07:00 |
|
tangxifan
|
392ab0f027
|
move duplicated codes on message printing to functions
|
2020-01-31 10:53:41 -07:00 |
|
tangxifan
|
afde9808da
|
add check codes for physical pb_graph_node and pb_graph_pin annotation
|
2020-01-31 10:47:05 -07:00 |
|
tangxifan
|
fdc304a0fb
|
fixed a bug in mapping pb_graph pins using rotation offset
|
2020-01-30 22:00:53 -07:00 |
|
tangxifan
|
02d6256e95
|
pass simple test on pb_type annotation for frac_lut5 architecture
|
2020-01-30 21:39:44 -07:00 |
|
tangxifan
|
007e1997e6
|
add pb_graph pin annotation
|
2020-01-30 19:40:40 -07:00 |
|
tangxifan
|
d62c9fe86f
|
adding pb_graph_node annotation
|
2020-01-30 16:40:13 -07:00 |
|
tangxifan
|
e48ab8cb44
|
move annotation source files to a separated folder
|
2020-01-30 13:37:41 -07:00 |
|
tangxifan
|
568ed120c2
|
change report naming fix-up to be XML format
|
2020-01-29 21:53:56 -07:00 |
|
tangxifan
|
f28ca3ffd0
|
add more echo to log
|
2020-01-29 18:58:57 -07:00 |
|
tangxifan
|
87f1ca1151
|
add naming fix-up report generation
|
2020-01-29 18:56:47 -07:00 |
|
tangxifan
|
2dc4c26257
|
add naming fix-up
|
2020-01-29 17:49:33 -07:00 |
|
tangxifan
|
8c86c0af04
|
add check netlist naming conflict command and functions
|
2020-01-29 16:23:41 -07:00 |
|
tangxifan
|
d2c47693f6
|
add check codes for mode bits annotation to pb_types and clean up utils source files
|
2020-01-29 14:29:00 -07:00 |
|
tangxifan
|
a4381563bc
|
move check codes to separated source files
|
2020-01-29 13:47:59 -07:00 |
|
tangxifan
|
b67358d2c5
|
add check codes for physical pb_type circuit model annotation
|
2020-01-29 12:56:49 -07:00 |