tangxifan
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8d6682c28b
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[test] fixed a bug when removing previous runs
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2022-08-25 16:20:18 -07:00 |
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tangxifan
|
fa790d50d4
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[script] fixed a bug on wrong path to the ace2 executable
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2022-08-23 10:53:44 -07:00 |
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tangxifan
|
bdb051f787
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[arch] update arch files
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2022-08-22 18:24:37 -07:00 |
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tangxifan
|
6c44f321e5
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[script] fixed a bug
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2022-08-22 18:24:26 -07:00 |
|
tangxifan
|
2bbf2f02c9
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[script] now return status on each arch upgrade task
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2022-08-22 18:23:00 -07:00 |
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tangxifan
|
b6e1175517
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[script] update doc and avoid modify README.MD when updating arch files
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2022-08-22 18:19:23 -07:00 |
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tangxifan
|
8d45903dc2
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[script] makefile for vpr arch
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2022-08-22 18:13:48 -07:00 |
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tangxifan
|
3c9c11d451
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[script] working on formatting
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2022-08-22 18:02:38 -07:00 |
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tangxifan
|
55e765a206
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[script] slight improve on formatting
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2022-08-22 18:00:14 -07:00 |
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tangxifan
|
4a7c3fce93
|
[script] debugging format
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2022-08-22 17:04:30 -07:00 |
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tangxifan
|
2f5ea0cabb
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[script] functional arch file converter; need to clean up formatting issues
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2022-08-22 16:40:49 -07:00 |
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tangxifan
|
4efc506762
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[script] now change to use minidom and debugging the child removal
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2022-08-22 16:33:49 -07:00 |
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tangxifan
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880d7122bf
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[script] complete code; start debugging on arch file converter
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2022-08-22 12:29:49 -07:00 |
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tangxifan
|
5134ea2233
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[script] save progress
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2022-08-22 11:00:46 -07:00 |
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tangxifan
|
a61d6a2685
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[script] developing arch converting script
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2022-08-22 10:34:29 -07:00 |
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tangxifan
|
c0b1d76a5e
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[script] change default tool paths for OpenFPGA flow scripts
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2022-08-18 11:02:21 -07:00 |
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tangxifan
|
6ce1d4804c
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[test] deploy new test case to basic regression tests
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2022-08-01 21:05:05 -07:00 |
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tangxifan
|
9ea4a7c90f
|
[script] fixed a bug
|
2022-08-01 19:18:41 -07:00 |
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tangxifan
|
8b17bf1b1c
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[test] add a new test case to validate that .act file is not required when power analysis flow is off
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2022-08-01 18:44:47 -07:00 |
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tangxifan
|
55c7b75ab6
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[script] even when power analysis mode is turned off, if users define a act file, still use it
|
2022-08-01 18:13:57 -07:00 |
root
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0da44ad1fc
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[script] now .act file is no longer required in openfpga_flow/task when power analysis option is off
|
2022-08-02 08:02:28 +08:00 |
|
tangxifan
|
35fe858035
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[test] fixed a few bugs
|
2022-07-28 12:06:16 -07:00 |
|
tangxifan
|
ca9122ddb9
|
[test] fixed a bug
|
2022-07-28 11:57:47 -07:00 |
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tangxifan
|
ec31e124b7
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[test] reworked test case on pcf2place
|
2022-07-28 11:51:56 -07:00 |
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tangxifan
|
23f98d6a3b
|
[engine] fixed a few bugs
|
2022-07-26 13:55:29 -07:00 |
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tangxifan
|
353de4546f
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[test] add 'write_fabric_io_info' command to test cases
|
2022-07-26 13:48:54 -07:00 |
taoli4rs
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347a29f27c
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Fix test name in basic regression test script.
|
2022-07-20 21:05:31 -07:00 |
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taoli4rs
|
3762a3aae4
|
Code clean up based on review.
|
2022-07-20 14:34:44 -07:00 |
|
taoli4rs
|
cfc0d08060
|
Add constrain_pin_location command in openfpga; add full flow test.
|
2022-07-20 11:51:00 -07:00 |
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tangxifan
|
4b9431b132
|
[test] avoid XML bitstream output when can go beyond github runners' disk space
|
2022-05-25 18:45:26 +08:00 |
|
tangxifan
|
9832722056
|
[test] now add QuickLogic memory bank to fpga bitstream regression tests
|
2022-05-25 11:42:32 +08:00 |
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tangxifan
|
86347a9d49
|
[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
|
2022-05-25 11:19:49 +08:00 |
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tangxifan
|
7d694acf32
|
[test] debugging basic reg test paths
|
2022-05-23 11:21:36 +08:00 |
|
tangxifan
|
b41cbad5d3
|
[test] force to run git diff under root directory
|
2022-05-23 10:32:43 +08:00 |
|
tangxifan
|
488a934097
|
[test] give abs path for git diff in basic regression tests
|
2022-05-23 09:12:33 +08:00 |
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tangxifan
|
0dc7caf3b7
|
[test] now regression test script supports remove all run dir through command-line options
|
2022-05-22 13:15:39 +08:00 |
|
tangxifan
|
751d87b8e3
|
[test] fix a bug in detect changes in golden netlists
|
2022-05-22 13:06:47 +08:00 |
|
tangxifan
|
6719a9aa26
|
[test] update golden netlists/testbenches etc.
|
2022-05-22 13:03:01 +08:00 |
ganeshgore
|
17c4e9a1bb
|
Merge branch 'master' into binder
|
2022-05-10 19:58:17 -06:00 |
|
tangxifan
|
d7e854eae7
|
[test] deploy new test to ci
|
2022-05-09 17:23:57 +08:00 |
|
tangxifan
|
7ed1548c6e
|
[arch] fixed a few bugs
|
2022-05-09 17:22:48 +08:00 |
|
tangxifan
|
9f56e61342
|
[arch] syntax
|
2022-05-09 17:13:57 +08:00 |
|
tangxifan
|
0afe3a6d33
|
[HDL] update dff map rules to support negative triggered ffs
|
2022-05-09 16:58:18 +08:00 |
|
tangxifan
|
22c4d72358
|
[test] add a test case to validate negative edge-triggered ff
|
2022-05-09 16:57:42 +08:00 |
|
tangxifan
|
9c7868cfab
|
[hdl] add a counter design which is triggered by negative edges
|
2022-05-09 16:41:21 +08:00 |
|
tangxifan
|
812af4f722
|
[arch] add arch that supports negative edge triggered flip-flop
|
2022-05-09 16:32:01 +08:00 |
|
tangxifan
|
c8ff3fc8dc
|
[test] add regression test to validate compilation of openfpga cell library files
|
2022-05-09 16:00:51 +08:00 |
|
tangxifan
|
d4992fd9ad
|
[HDL] Add a multi-mode ff which can support posedge and negedge
|
2022-05-09 15:52:17 +08:00 |
|
Ganesh Gore
|
daae02a614
|
Minor documentation update
|
2022-05-08 13:03:16 -06:00 |
|
Ganesh Gore
|
522982c9ba
|
Adde vtr_benchmarks_template for demo
|
2022-05-06 22:40:36 -06:00 |