tangxifan
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80bb2baae5
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start verification and bug fixing
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2020-02-28 14:29:01 -07:00 |
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tangxifan
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542fadaaae
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allow users to use VPR critical path delay in OpenFPGA simulation
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2020-02-28 12:10:27 -07:00 |
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tangxifan
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de8425874c
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use user defined critical path delay in SDC generation
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2020-02-28 11:24:39 -07:00 |
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tangxifan
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092e10afda
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bring pnr sdc generator online and fixed minor bugs in bitstream writing
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2020-02-28 11:14:50 -07:00 |
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tangxifan
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e45fa18c4c
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adapt PnR SDC writer
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2020-02-28 10:06:35 -07:00 |
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tangxifan
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89c51b70e3
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split sdc option into two categories which will be called by different commands
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2020-02-28 09:48:58 -07:00 |
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tangxifan
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fdcb982903
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adapt pnr sdc grid writer
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2020-02-27 21:06:33 -07:00 |
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tangxifan
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b4ed931ac6
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adapt sdc routing writer
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2020-02-27 20:35:56 -07:00 |
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tangxifan
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d136ac236f
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adapt sdc memory utils
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2020-02-27 19:39:57 -07:00 |
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tangxifan
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78476ca774
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adapt sdc writer utils
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2020-02-27 19:36:28 -07:00 |
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tangxifan
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8322b1623d
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start porting SDC generator
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2020-02-27 19:30:36 -07:00 |
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tangxifan
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fc509aa2c1
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Merge branch 'refactoring' into dev
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2020-02-27 18:03:21 -07:00 |
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tangxifan
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65c81e14b2
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add simulation ini file writer
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2020-02-27 18:01:47 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
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tangxifan
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9b769cd8e4
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bug fix for using renamed i/o names
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2020-02-27 16:37:20 -07:00 |
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tangxifan
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b010fc1983
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add warning to force formal_verification_top_netlist enabled
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2020-02-27 13:28:21 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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77529f4957
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adapt top Verilog testbench generation
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2020-02-26 21:30:21 -07:00 |
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tangxifan
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bb671acac3
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add formal random Verilog testbench generation
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2020-02-26 20:58:16 -07:00 |
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tangxifan
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e9adb4fdbc
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add preconfig top module Verilog generation
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2020-02-26 20:38:01 -07:00 |
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tangxifan
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b3796b0818
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build io location map
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2020-02-26 19:58:18 -07:00 |
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tangxifan
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25e0583636
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add io location map data structure and start porting verilog testbench generator
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2020-02-26 17:10:57 -07:00 |
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tangxifan
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1fa36c22d3
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Merge branch 'refactoring' into dev
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2020-02-26 11:42:50 -07:00 |
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tangxifan
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410dcf6ab6
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debugged LUT bitstream
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2020-02-26 11:42:18 -07:00 |
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tangxifan
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a26d31b87f
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make write bitstream online
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2020-02-26 11:09:23 -07:00 |
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tangxifan
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759758421d
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found the bug in physical pb mode bits and fixed
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2020-02-25 23:45:49 -07:00 |
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tangxifan
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075264e3e3
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debugging LUT bitstream generation
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2020-02-25 23:29:16 -07:00 |
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tangxifan
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4024ed63cb
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add truth table build up for physical LUTs
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2020-02-25 22:39:42 -07:00 |
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tangxifan
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2dd80e4830
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add more methods to acquire physical truth table from physical pb
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2020-02-25 21:21:44 -07:00 |
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tangxifan
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ca038857d3
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add lut physical truth table to physical pb
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2020-02-25 13:34:13 -07:00 |
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tangxifan
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2d86a02358
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refactored LUT bitstream generation to use vtr logic
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2020-02-25 12:45:13 -07:00 |
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tangxifan
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2c44c70557
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bring pb interconnection bitstream generation online
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2020-02-25 00:28:06 -07:00 |
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tangxifan
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04c69d30c2
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start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
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2020-02-24 19:38:02 -07:00 |
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tangxifan
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8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
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712eeb1340
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bring bitstream generator for routing modules online
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2020-02-23 22:09:46 -07:00 |
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tangxifan
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86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |
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tangxifan
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8723007f68
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Bring mux bitstream generation online
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2020-02-23 20:53:24 -07:00 |
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tangxifan
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51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
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0a01e71ba0
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Merge branch 'refactoring' into dev
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2020-02-22 22:11:27 -07:00 |
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tangxifan
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9583731531
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add results saver for lb router
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2020-02-22 22:10:32 -07:00 |
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tangxifan
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91338994c8
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Merge branch 'refactoring' into dev
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2020-02-22 18:51:51 -07:00 |
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tangxifan
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921bf7dd7b
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use constant in device annotation
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2020-02-21 20:45:22 -07:00 |
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tangxifan
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926e429374
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add save repacking results in physical pb
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2020-02-21 20:39:49 -07:00 |
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tangxifan
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12f2888c7c
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add physical pb data structure and basic allocator
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2020-02-21 17:47:27 -07:00 |
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tangxifan
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b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
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1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
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0b0e00b5f4
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debugging the LbRouter
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2020-02-20 21:56:15 -07:00 |
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tangxifan
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4abaef14b5
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |