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1056 Commits

Author SHA1 Message Date
tangxifan 7327850cf3 [Test] Deploy the fabric key test case for ql memory bank to basic regression tests 2021-09-21 15:43:54 -07:00
tangxifan dc2d1d1c3c [Test] Add a new test case to validate the correctness of fabric key file for ql memory bank 2021-09-21 15:42:20 -07:00
tangxifan d36d1ebee2 [HDL] Temporarily disable WLR func in primitive HDL modeling 2021-09-20 17:07:51 -07:00
tangxifan 0450d57d82 [Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR 2021-09-20 16:05:01 -07:00
tangxifan 3f6ac41868 [Test] Deploy the WLR test to the basic regression tests 2021-09-20 11:21:58 -07:00
tangxifan 60fc3ab36c [Test] Added a new test case for the WLR memory bank 2021-09-20 11:20:36 -07:00
tangxifan 5c1c428ea5 [HDL] Updated cell library with the SRAM cell with Read Enable signal 2021-09-20 11:13:36 -07:00
tangxifan cd2978a434 [Arch] Added a new architecture example which shows how to use the memory bank with readback functionality 2021-09-20 11:13:02 -07:00
tangxifan 81a2ad58df [Test] Deploy the ql memory bank test case to basic regression tests (run on CI) 2021-09-09 13:48:30 -07:00
tangxifan b82cfdf555 [Test] Add the QL memory bank test to regression test cases 2021-09-09 09:29:21 -07:00
tangxifan 6be3c64f1c [Arch] Add an example architecture using the physical design friendly memory bank organization 2021-09-09 09:22:27 -07:00
tangxifan 6adf439081 Merge remote-tracking branch 'upstream/master' 2021-09-01 14:19:00 -07:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
komaljaved-rs be14e4f448 added design_variables.yml 2021-07-01 16:31:42 +05:00
komaljaved-rs 6559f71082 added ci_scripts 2021-07-01 15:07:37 +05:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 83d177b13b [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00
tangxifan 5f5a03f17f [Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches 2021-06-29 18:28:38 -06:00
tangxifan 2c1692e6dc [Test] Bug fix 2021-06-29 17:54:25 -06:00
tangxifan 4fb34642ca [Script] Add a new example script for global tile clock running full testbench 2021-06-29 17:53:56 -06:00