Commit Graph

849 Commits

Author SHA1 Message Date
tangxifan ab6f1a5461 add mux output ids for mux_graph 2019-08-26 21:21:50 -06:00
tangxifan de8a6bc833 update regression tests 2019-08-26 21:00:15 -06:00
Ganesh Gore 38e1d1bbff Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-25 21:41:38 -06:00
tangxifan b6617a5adf fix bugs in verilog comment lines 2019-08-25 16:37:46 -06:00
tangxifan 14db2bf1a9 minor fixing on comment 2019-08-25 16:35:49 -06:00
tangxifan 706b7f3427 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-25 15:52:04 -06:00
tangxifan 1cfc117b32 developed verilog instance writer. refactoring on mux ongoing 2019-08-25 15:47:57 -06:00
tangxifan 056c45321b plug in module manager 2019-08-25 15:44:31 -06:00
tangxifan 8fc258cc93 develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-25 15:33:37 -06:00
tangxifan c43fabb43c developed verilog instance writer. refactoring on mux ongoing 2019-08-25 10:31:45 -06:00
Ganesh Gore 7a3ff94116 Added blif task in travis script 2019-08-25 01:28:21 -06:00
Ganesh Gore 937ebd1b85 Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev 2019-08-25 00:53:18 -06:00
Ganesh Gore c4180fad6d Added .gitignore to build docs locally 2019-08-25 00:49:04 -06:00
Ganesh Gore 632c9d6976 Added python execution path in config file 2019-08-25 00:42:48 -06:00
Ganesh Gore f558437ae1 Added task for vpr_blif flow 2019-08-25 00:23:39 -06:00
tangxifan fe7dfd59c3 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-24 23:54:37 -06:00
tangxifan 63f40f48fa develop and plug mux_lib_builder, refactoring the mux submodule generation 2019-08-24 19:23:33 -06:00
tangxifan 27b619554d add stats for verilog modules 2019-08-23 20:23:42 -06:00
tangxifan ad06e9c98c plug in module manager 2019-08-23 20:23:41 -06:00
tangxifan 39853408dd add recursive global port searching for circuit library 2019-08-23 20:23:41 -06:00
tangxifan fcb31e4c24 add stats for verilog modules 2019-08-23 18:41:16 -06:00
tangxifan 8eebca9daa plug in module manager 2019-08-23 17:39:29 -06:00
tangxifan 1b4de2b335 Merge branch 'refactoring' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-23 16:37:24 -06:00
tangxifan 37a092e885 add recursive global port searching for circuit library 2019-08-23 16:36:30 -06:00
Ganesh Gore 2e3f906d40 Solved bug in travis script file 2019-08-23 16:03:21 -06:00
tangxifan 3fb3082447 add more tests 2019-08-23 14:10:01 -06:00
tangxifan e55c6d5b41 add more tests 2019-08-23 14:09:20 -06:00
tangxifan 95f8fea299 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-08-23 13:45:30 -06:00
tangxifan ede29aa656 Merge branch 'refactoring' into dev 2019-08-23 13:42:10 -06:00
Ganesh Gore 52d6a9e979 Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-23 13:41:29 -06:00
tangxifan 931b042750 refactoring module manager 2019-08-23 12:52:01 -06:00
Ganesh Gore 82a186bf7c Added python3.5 in travis script 2019-08-23 12:45:17 -06:00
Ganesh Gore 28dde899db Updated Architecture Template 2019-08-23 12:44:45 -06:00
tangxifan 520630c5e2 add more testing tasks 2019-08-23 10:16:52 -06:00
tangxifan 732e24767f developing module manager 2019-08-22 23:49:35 -06:00
Ganesh Gore 6e7de16ad4 Solved bug in commnad rearrangement 2019-08-22 23:41:25 -06:00
Ganesh Gore 89589ddc1c Merge remote-tracking branch 'origin/ganesh_dev' into dev 2019-08-22 18:46:51 -06:00
Ganesh Gore 4189ada1eb Fixed run test file 2019-08-22 17:31:46 -06:00
Ganesh Gore 5027f9c4b3 Added test mode script in travis 2019-08-22 17:03:56 -06:00
Ganesh Gore 8f80cb3c24 Added Sample script to run blif VPR 2019-08-22 17:02:12 -06:00
Ganesh Gore 77e2a7bca3 Added execution time logs in flow script 2019-08-22 17:01:38 -06:00
Ganesh Gore 30cbe38d3d Added Test Modes - Added blif VPR Option 2019-08-22 17:00:59 -06:00
Ganesh Gore d5ce1b557e Made thread logs prettier 2019-08-22 16:56:58 -06:00
tangxifan 3f45e6cc87 remove dead codes for essential gates code generation 2019-08-22 10:01:52 -06:00
tangxifan 43de2d7636 some tuning on Verilog port formatting 2019-08-21 23:47:50 -06:00
tangxifan 1be5632e92 minor tuning on the delay assignment 2019-08-21 23:11:54 -06:00
tangxifan 7b0c55ce15 try to reduce precision in timing assignment of Verilog netlist (travis iverilog was not happy) 2019-08-21 22:45:48 -06:00
tangxifan 5a40c6713d managed to plug in refactored essential gates, dead codes to be removed 2019-08-21 21:50:26 -06:00
tangxifan d8eb9866a0 refactored gate verilog generation 2019-08-21 18:49:48 -06:00
tangxifan b08ff465c9 refactored pass-gate verilog generation 2019-08-21 17:33:16 -06:00