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OpenFPGA
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3,970 Commits 71 Branches 8 Tags 105 MiB
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1059 Commits

Author SHA1 Message Date
Andrew Pond a486c2690f Merge branch 'timing_annotation' into arch_exploration 2021-09-28 16:22:13 -06:00
Andrew Pond cebcdba4d4 added fpgatoolperf vexriscv src 2021-09-28 13:32:41 -06:00
Andrew Pond 0783072be7 fixed errors 2021-08-16 16:12:51 -06:00
Andrew Pond 73854bbe66 bram timing update 2021-07-29 12:32:52 -06:00
Andrew Pond cb0dbd6f2f responding to Xifan's comments in PR 2021-07-26 17:40:34 -06:00
Andrew Pond e39e9b8c26 finishing touches for PR 2021-07-23 12:08:32 -06:00
Andrew Pond ce71466b32 fixed bram CI error 2021-07-23 11:16:26 -06:00
Andrew Pond 05c4a253cc fixed CI errors 2021-07-22 16:39:44 -06:00
Andrew Pond 29f67479cc yosys techlib directory restructure 2021-07-22 15:14:14 -06:00
Andrew Pond 6cb51d1e7d timing files renamed 2021-07-21 14:12:32 -06:00
Andrew Pond 60ac09d315 removed duplicate yosys script 2021-07-21 08:09:20 -06:00
Andrew Pond 805053f4be created timing annotation file 2021-07-20 11:45:35 -06:00
Andrew Pond afea5bb44c started updating timings 2021-07-19 10:48:55 -06:00
Andrew Pond a9755c4dec started modifying arch files 2021-07-16 09:09:25 -06:00
Andrew Pond b3870b3107
Merge branch 'master' into bram_changes 2021-07-06 15:33:40 -06:00
Andrew Pond 6445507ddf pmux2mux yosys script change 2021-07-06 14:19:28 -06:00
Andrew Pond 1409b3e855 pmux2mux.v path change 2021-07-06 12:25:51 -06:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00
tangxifan fd85f956c9 [Arch] Update k4n4 arch with true multi-mode flip-flop 2021-07-02 11:08:39 -06:00
tangxifan 0b6a9b06f5 [Benchmark] Reorganize counter benchmarks. Move them to a directory and give specific naming regarding their functionality 2021-07-02 10:39:07 -06:00
Ganesh Gore 1de1f2f2e2 [FLOW] Variable in capital case 2021-07-01 22:26:00 -06:00
Ganesh Gore 81f9dff9ff [Flow] Allows benchmark specific var declaraton 2021-07-01 22:19:53 -06:00
Andrew Pond 46935f9f23 started bram branch 2021-07-01 17:12:54 -06:00
ANDREW HARRIS POND 1d281765ea fixed tab spacing 2021-07-01 16:42:04 -06:00
ANDREW HARRIS POND 808821bb8c fixed errors 2021-07-01 16:40:03 -06:00
ANDREW HARRIS POND 006b54c4bc ready for merge 2021-07-01 15:35:39 -06:00
ANDREW HARRIS POND 8513b8a4ff Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench 2021-07-01 15:29:39 -06:00
ANDREW HARRIS POND 2567fbee05 ready to merge 2021-07-01 15:28:59 -06:00
tangxifan 04ceeefb0a
Merge branch 'master' into verilog_testbench 2021-07-01 14:43:26 -06:00
ANDREW HARRIS POND db9231c225 tests failing with initial blocks 2021-07-01 13:52:28 -06:00
Andrew Pond fab2b069f0 added signal gen regression test to shell script 2021-06-30 16:18:09 -06:00
tangxifan a898537474 [Benchmark] Remove redundant post-synthesis netlist for ``adder_8`` 2021-06-30 15:29:13 -06:00
tangxifan 83d177b13b [Test] Deploy the newly added adder benchmarks to tests 2021-06-30 15:14:24 -06:00
tangxifan 4d4577bb83 [Benchmark] Added multiple adder benchmarks to have better coverage in testing FPGA arch with adders 2021-06-30 15:13:47 -06:00
tangxifan 9eeec05a1f [Test] Bug fix 2021-06-29 19:55:07 -06:00
tangxifan f32ffb6d61 [Test] Bug fix 2021-06-29 18:51:28 -06:00
tangxifan 56b0428eba [Misc] Bug fix 2021-06-29 18:48:19 -06:00
tangxifan c6089385b0 [Misc] Bug fix 2021-06-29 18:34:41 -06:00