Merge branch 'timing_annotation' into arch_exploration
This commit is contained in:
Andrew Pond
commit
a486c2690f
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@ -1,102 +0,0 @@
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|||
# Yosys synthesis script for ${TOP_MODULE}
|
||||
|
||||
#########################
|
||||
# Parse input files
|
||||
#########################
|
||||
# Read verilog files
|
||||
${READ_VERILOG_FILE}
|
||||
# Read technology library
|
||||
read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG}
|
||||
|
||||
#########################
|
||||
# Prepare for synthesis
|
||||
#########################
|
||||
# Identify top module from hierarchy
|
||||
hierarchy -check -top ${TOP_MODULE}
|
||||
# - Convert process blocks to AST
|
||||
proc
|
||||
# Flatten all the gates/primitives
|
||||
flatten
|
||||
# Identify tri-state buffers from 'z' signal in AST
|
||||
# with follow-up optimizations to clean up AST
|
||||
tribuf -logic
|
||||
opt_expr
|
||||
opt_clean
|
||||
# demote inout ports to input or output port
|
||||
# with follow-up optimizations to clean up AST
|
||||
deminout
|
||||
opt
|
||||
|
||||
opt_expr
|
||||
opt_clean
|
||||
check
|
||||
opt
|
||||
wreduce -keepdc
|
||||
peepopt
|
||||
pmuxtree
|
||||
opt_clean
|
||||
|
||||
########################
|
||||
# Map multipliers
|
||||
# Inspired from synth_xilinx.cc
|
||||
#########################
|
||||
# Avoid merging any registers into DSP, reserve memory port registers first
|
||||
memory_dff
|
||||
wreduce t:$mul
|
||||
techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS}
|
||||
select a:mul2dsp
|
||||
setattr -unset mul2dsp
|
||||
opt_expr -fine
|
||||
wreduce
|
||||
select -clear
|
||||
chtype -set $mul t:$__soft_mul# Extract arithmetic functions
|
||||
|
||||
#########################
|
||||
# Run coarse synthesis
|
||||
#########################
|
||||
# Run a tech map with default library
|
||||
techmap
|
||||
alumacc
|
||||
share
|
||||
opt
|
||||
fsm
|
||||
# Run a quick follow-up optimization to sweep out unused nets/signals
|
||||
opt -fast
|
||||
# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells
|
||||
memory -nomap
|
||||
opt_clean
|
||||
|
||||
|
||||
#########################
|
||||
# Map muxes to pmuxes
|
||||
#########################
|
||||
techmap -map +/pmux2mux.v
|
||||
|
||||
#########################
|
||||
# Map flip-flops
|
||||
#########################
|
||||
techmap -map ${YOSYS_DFF_MAP_VERILOG}
|
||||
opt_expr -mux_undef
|
||||
simplemap
|
||||
opt_expr
|
||||
opt_merge
|
||||
opt_rmdff
|
||||
opt_clean
|
||||
opt
|
||||
|
||||
#########################
|
||||
# Map LUTs
|
||||
#########################
|
||||
abc -lut ${LUT_SIZE}
|
||||
|
||||
#########################
|
||||
# Check and show statisitics
|
||||
#########################
|
||||
hierarchy -check
|
||||
stat
|
||||
|
||||
#########################
|
||||
# Output netlists
|
||||
#########################
|
||||
opt_clean -purge
|
||||
write_blif ${OUTPUT_BLIF}
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||||
|
|
@ -1,6 +1,6 @@
|
|||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
|
@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
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|||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
|
@ -71,4 +71,4 @@ write_analysis_sdc --file ./SDC_analysis
|
|||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# Run VPR for the 'and' design
|
||||
#--write_rr_graph example_rr_graph.xml
|
||||
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
|
||||
|
||||
# Read OpenFPGA architecture definition
|
||||
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
|
||||
|
||||
# Read OpenFPGA simulation settings
|
||||
read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
|
||||
|
||||
# Annotate the OpenFPGA architecture to VPR data base
|
||||
# to debug use --verbose options
|
||||
link_openfpga_arch --sort_gsb_chan_node_in_edges
|
||||
|
||||
# Check and correct any naming conflicts in the BLIF netlist
|
||||
check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
|
||||
|
||||
# Apply fix-up to clustering nets based on routing results
|
||||
pb_pin_fixup --verbose
|
||||
|
||||
# Apply fix-up to Look-Up Table truth tables based on packing results
|
||||
lut_truth_table_fixup
|
||||
|
||||
# Build the module graph
|
||||
# - Enabled compression on routing architecture modules
|
||||
# - Enable pin duplication on grid modules
|
||||
build_fabric --compress_routing #--verbose
|
||||
|
||||
# Write the fabric hierarchy of module graph to a file
|
||||
# This is used by hierarchical PnR flows
|
||||
write_fabric_hierarchy --file ./fabric_hierarchy.txt
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||||
|
||||
# Repack the netlist to physical pbs
|
||||
# This must be done before bitstream generator and testbench generation
|
||||
# Strongly recommend it is done after all the fix-up have been applied
|
||||
repack #--verbose
|
||||
|
||||
# Build the bitstream
|
||||
# - Output the fabric-independent bitstream to a file
|
||||
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
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||||
|
||||
# Build fabric-dependent bitstream
|
||||
build_fabric_bitstream --verbose
|
||||
|
||||
# Write fabric-dependent bitstream
|
||||
write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION}
|
||||
|
||||
# Write the Verilog netlist for FPGA fabric
|
||||
# - Enable the use of explicit port mapping in Verilog netlist
|
||||
write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose
|
||||
|
||||
# Write the Verilog testbench for FPGA fabric
|
||||
# - We suggest the use of same output directory as fabric Verilog netlists
|
||||
# - Must specify the reference benchmark file if you want to output any testbenches
|
||||
# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
|
||||
# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
|
||||
# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
|
||||
write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION}
|
||||
|
||||
# Write the SDC files for PnR backend
|
||||
# - Turn on every options here
|
||||
write_pnr_sdc --file ./SDC
|
||||
|
||||
# Write SDC to disable timing for configure ports
|
||||
write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
|
||||
|
||||
# Write the SDC to run timing analysis for a mapped FPGA fabric
|
||||
write_analysis_sdc --file ./SDC_analysis
|
||||
|
||||
# Finish and exit OpenFPGA
|
||||
exit
|
||||
|
||||
# Note :
|
||||
# To run verification at the end of the flow maintain source in ./SRC directory
|
||||
{"mode":"full","isActive":false}
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
Naming convention for timing annotation files
|
||||
Convention follows the VPR architecture file naming convention, with some extra detail appended to the end.
|
||||
|
||||
k<lut_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
|
||||
The keyword 'frac' is to specify if fracturable LUT is used or not.
|
||||
The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch).
|
||||
N<le_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
|
||||
tileable: If the routing architecture is tileable or not.
|
||||
The keyword 'IO' specifies if the I/O tile is tileable or not
|
||||
fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable
|
||||
adder_chain: If hard adder/carry chain is used inside CLBs
|
||||
register_chain: If shift register chain is used inside CLBs
|
||||
scan_chain: If scan chain testing infrastructure is used inside CLBs
|
||||
__mem<mem_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
|
||||
__dsp<dsp_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
|
||||
aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
|
||||
multi_io_capacity: If I/O capacity is different on each side of FPGAs.
|
||||
reduced_io: If I/Os only appear a certain or multiple sides of FPGAs
|
||||
registerable_io: If I/Os are registerable (can be either combinational or sequential)
|
||||
<feature_size>: The technology node which the delay numbers are extracted from.
|
||||
TileOrgz: How tile is organized.
|
||||
Top-left (Tl): the pins of a tile are placed on the top side and left side only
|
||||
Top-right (Tr): the pins of a tile are placed on the top side and right side only
|
||||
Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only
|
||||
GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks
|
||||
Other features are used in naming should be listed here.
|
||||
|
||||
tt/ff/ss: timing coners specified at the end of the file name. Each file under the specific architecture is tied to a certain corner, as the timing values will change with the corner.
|
||||
|
|
@ -1,33 +1,17 @@
|
|||
L1_SB_MUX_DELAY: 1.44e-9
|
||||
L2_SB_MUX_DELAY: 1.44e-9
|
||||
L4_SB_MUX_DELAY: 1.44e-9
|
||||
CB_MUX_DELAY: 1.38e-9
|
||||
L1_WIRE_R: 100
|
||||
L1_WIRE_C: 1e-12
|
||||
L2_WIRE_R: 100
|
||||
L2_WIRE_C: 1e-12
|
||||
L4_WIRE_R: 100
|
||||
L4_WIRE_C: 1e-12
|
||||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FF_D_DELAY: 1.14e-9
|
||||
LUT_OUT1_TO_FF_D_DELAY: 0.56e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
LUT3_DELAY: 0.92e-9
|
||||
LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9
|
||||
LUT4_DELAY: 1.21e-9
|
||||
LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9
|
||||
LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
|
||||
LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
|
||||
LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
REGIN_TO_FF0_DELAY: 1.12e-9
|
||||
FF0_TO_FF1_DELAY: 0.56e-9
|
||||
|
||||
CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
|
|
@ -48,15 +32,6 @@ ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
|
|||
|
||||
|
||||
|
||||
################# MULT9 Delays #################
|
||||
|
||||
MULT9_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT9_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT9_B2Y_DELAY_MIN: 0.776e-9
|
||||
|
||||
|
||||
|
||||
################# MULT18 Delays #################
|
||||
|
||||
MULT18_A2Y_DELAY_MAX: 1.523e-9
|
||||
|
|
@ -79,7 +54,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
|
|||
DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
|
||||
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
|
||||
|
||||
MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
|
||||
MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
|
||||
LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
|
||||
LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
|
||||
CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
|
||||
CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
|
||||
|
||||
|
||||
|
||||
################# Adder Delays #################
|
||||
|
||||
ADDER_CIN2OUT_DELAY: 1.21e-9
|
||||
ADDER_CIN2COUT_DELAY: 1.21e-9
|
||||
ADDER_IN2OUT_DELAY: 1.21e-9
|
||||
ADDER_IN2COUT_DELAY: 1.21e-9
|
||||
|
||||
ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
|
||||
ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
|
||||
|
||||
|
||||
|
||||
################# BRAM Delays #################
|
||||
|
||||
DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
|
||||
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
|
||||
|
||||
MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
|
||||
MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12
|
||||
MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12
|
||||
MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12
|
||||
MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12
|
||||
BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
INPAD_DELAY: 0.11e-9
|
||||
OUTPAD_DELAY: 0.11e-9
|
||||
FF_T_SETUP: 0.39e-9
|
||||
FF_T_CLK2Q: 0.43e-9
|
||||
LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9
|
||||
LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9
|
||||
FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9
|
||||
LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE
|
||||
LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE
|
||||
LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE
|
||||
|
||||
CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE
|
||||
|
||||
CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE
|
||||
|
||||
|
||||
|
||||
################# Adder Delays #################
|
||||
|
||||
ADDER_CIN2OUT_DELAY: 1.21e-9
|
||||
ADDER_CIN2COUT_DELAY: 1.21e-9
|
||||
ADDER_IN2OUT_DELAY: 1.21e-9
|
||||
ADDER_IN2COUT_DELAY: 1.21e-9
|
||||
|
||||
ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12
|
||||
ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12
|
||||
|
||||
|
||||
|
||||
################# MULT18 Delays #################
|
||||
|
||||
MULT18_A2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_A2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_B2Y_DELAY_MAX: 1.523e-9
|
||||
MULT18_B2Y_DELAY_MIN: 0.776e-9
|
||||
MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE
|
||||
MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE
|
||||
MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE
|
||||
MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE
|
||||
MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE
|
||||
MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
// Basic DFF
|
||||
module \$_DFF_P_ (D, C, Q);
|
||||
input D;
|
||||
input C;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C));
|
||||
endmodule
|
||||
|
||||
// Async active-high reset
|
||||
module \$_DFF_PP0_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R));
|
||||
endmodule
|
||||
|
||||
// Async active-high set
|
||||
module \$_DFF_PP1_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R));
|
||||
endmodule
|
||||
|
||||
// Async active-low reset
|
||||
module \$_DFF_PN0_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R));
|
||||
endmodule
|
||||
|
||||
// Async active-low set
|
||||
module \$_DFF_PN1_ (D, C, R, Q);
|
||||
input D;
|
||||
input C;
|
||||
input R;
|
||||
output Q;
|
||||
parameter _TECHMAP_WIREINIT_Q_ = 1'bx;
|
||||
dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R));
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
bram $__MY_DPRAM_128x8
|
||||
init 0
|
||||
abits 7
|
||||
dbits 8
|
||||
groups 2
|
||||
ports 1 1
|
||||
wrmode 1 0
|
||||
enable 1 1
|
||||
transp 0 0
|
||||
clocks 1 1
|
||||
clkpol 1 1
|
||||
endbram
|
||||
|
||||
match $__MY_DPRAM_128x8
|
||||
min efficiency 0
|
||||
make_transp
|
||||
endmatch
|
||||
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
module $__MY_DPRAM_128x8 (
|
||||
output [0:7] B1DATA,
|
||||
input CLK1,
|
||||
input [0:6] B1ADDR,
|
||||
input [0:6] A1ADDR,
|
||||
input [0:7] A1DATA,
|
||||
input A1EN,
|
||||
input B1EN );
|
||||
|
||||
generate
|
||||
dpram_128x8 #() _TECHMAP_REPLACE_ (
|
||||
.clk (CLK1),
|
||||
.wen (A1EN),
|
||||
.waddr (A1ADDR),
|
||||
.data_in (A1DATA),
|
||||
.ren (B1EN),
|
||||
.raddr (B1ADDR),
|
||||
.data_out (B1DATA) );
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,58 +1,58 @@
|
|||
//-----------------------------
|
||||
// Dual-port RAM 128x8 bit (1Kbit)
|
||||
// Core logic
|
||||
//-----------------------------
|
||||
module dpram_128x8_core (
|
||||
input wclk,
|
||||
input wen,
|
||||
input [0:6] waddr,
|
||||
input [0:7] data_in,
|
||||
input rclk,
|
||||
input ren,
|
||||
input [0:6] raddr,
|
||||
output [0:7] data_out );
|
||||
|
||||
reg [0:7] ram[0:127];
|
||||
reg [0:7] internal;
|
||||
|
||||
assign data_out = internal;
|
||||
|
||||
always @(posedge wclk) begin
|
||||
if(wen) begin
|
||||
ram[waddr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rclk) begin
|
||||
if(ren) begin
|
||||
internal <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// Dual-port RAM 128x8 bit (1Kbit) wrapper
|
||||
// where the read clock and write clock
|
||||
// are combined to a unified clock
|
||||
//-----------------------------
|
||||
module dpram_128x8 (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input [0:6] waddr,
|
||||
input [0:6] raddr,
|
||||
input [0:7] data_in,
|
||||
output [0:7] data_out );
|
||||
|
||||
dpram_128x8_core memory_0 (
|
||||
.wclk (clk),
|
||||
.wen (wen),
|
||||
.waddr (waddr),
|
||||
.data_in (data_in),
|
||||
.rclk (clk),
|
||||
.ren (ren),
|
||||
.raddr (raddr),
|
||||
.data_out (data_out) );
|
||||
|
||||
endmodule
|
||||
//-----------------------------
|
||||
// Dual-port RAM 128x8 bit (1Kbit)
|
||||
// Core logic
|
||||
//-----------------------------
|
||||
module dpram_128x8_core (
|
||||
input wclk,
|
||||
input wen,
|
||||
input [0:6] waddr,
|
||||
input [0:7] data_in,
|
||||
input rclk,
|
||||
input ren,
|
||||
input [0:6] raddr,
|
||||
output [0:7] data_out );
|
||||
|
||||
reg [0:7] ram[0:127];
|
||||
reg [0:7] internal;
|
||||
|
||||
assign data_out = internal;
|
||||
|
||||
always @(posedge wclk) begin
|
||||
if(wen) begin
|
||||
ram[waddr] <= data_in;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge rclk) begin
|
||||
if(ren) begin
|
||||
internal <= ram[raddr];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
//-----------------------------
|
||||
// Dual-port RAM 128x8 bit (1Kbit) wrapper
|
||||
// where the read clock and write clock
|
||||
// are combined to a unified clock
|
||||
//-----------------------------
|
||||
module dpram_128x8 (
|
||||
input clk,
|
||||
input wen,
|
||||
input ren,
|
||||
input [0:6] waddr,
|
||||
input [0:6] raddr,
|
||||
input [0:7] data_in,
|
||||
output [0:7] data_out );
|
||||
|
||||
dpram_128x8_core memory_0 (
|
||||
.wclk (clk),
|
||||
.wen (wen),
|
||||
.waddr (waddr),
|
||||
.data_in (data_in),
|
||||
.rclk (clk),
|
||||
.ren (ren),
|
||||
.raddr (raddr),
|
||||
.data_out (data_out) );
|
||||
|
||||
endmodule
|
||||
|
|
@ -7,13 +7,14 @@ PYTHON_EXEC=python3.8
|
|||
# OpenFPGA Shell with VPR8
|
||||
##############################################
|
||||
echo -e "Micro benchmark regression tests";
|
||||
run-task benchmark_sweep/counter --debug --show_thread_logs
|
||||
run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
# run-task benchmark_sweep/counter --debug --show_thread_logs
|
||||
# run-task benchmark_sweep/mac_units --debug --show_thread_logs
|
||||
|
||||
# Verify MCNC big20 benchmark suite with ModelSim
|
||||
# Please make sure you have ModelSim installed in the environment
|
||||
# Otherwise, it will fail
|
||||
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
# # Verify MCNC big20 benchmark suite with ModelSim
|
||||
# # Please make sure you have ModelSim installed in the environment
|
||||
# # Otherwise, it will fail
|
||||
# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
|
||||
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
|
||||
|
||||
run-task benchmark_sweep/signal_gen --debug --show_thread_logs
|
||||
run-task benchmark_sweep/processor --debug --show_thread_logs
|
||||
|
|
|
|||
|
|
@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_
|
|||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=3x2
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
|
||||
yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt
|
||||
yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
|
||||
|
|
|
|||
|
|
@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
|
|||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
# Yosys script parameters
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
|
||||
yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v
|
||||
yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v
|
||||
yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=yosys_vpr
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=auto
|
||||
openfpga_fast_configuration=
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v
|
||||
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = picorv32
|
||||
bench0_chan_width = 300
|
||||
bench1_top = VexRiscv
|
||||
bench1_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
|
|
@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
|
|||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
|
||||
openfpga_vpr_device_layout=
|
||||
openfpga_clock_modeling=ideal
|
||||
openfpga_fast_configuration=
|
||||
|
||||
[ARCHITECTURES]
|
||||
|
|
|
|||
|
|
@ -1 +0,0 @@
|
|||
/home/apond/sofa/SCRIPT/skywater_openfpga_task
|
||||
|
|
@ -1,620 +0,0 @@
|
|||
<!--
|
||||
Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
|
||||
|
||||
- 40 nm technology
|
||||
- General purpose logic block:
|
||||
K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared)
|
||||
with optionally registered outputs
|
||||
- Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
|
||||
|
||||
Authors: Xifan Tang
|
||||
-->
|
||||
<architecture>
|
||||
<!--
|
||||
ODIN II specific config begins
|
||||
Describes the types of user-specified netlist blocks (in blif, this corresponds to
|
||||
".model [type_of_block]") that this architecture supports.
|
||||
|
||||
Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
|
||||
already special structures in blif (.names, .input, .output, and .latch)
|
||||
that describe them.
|
||||
-->
|
||||
<models>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="io">
|
||||
<input_ports>
|
||||
<port name="outpad"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="inpad"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for I/O to be used in the physical mode of io block -->
|
||||
<model name="frac_lut4">
|
||||
<input_ports>
|
||||
<port name="in"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="lut3_out"/>
|
||||
<port name="lut4_out"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dff">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dffr">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="R" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
<!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
|
||||
<model name="dffrn">
|
||||
<input_ports>
|
||||
<port name="D" clock="C"/>
|
||||
<port name="RN" clock="C"/>
|
||||
<port name="C" is_clock="1"/>
|
||||
</input_ports>
|
||||
<output_ports>
|
||||
<port name="Q" clock="C"/>
|
||||
</output_ports>
|
||||
</model>
|
||||
</models>
|
||||
<tiles>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<tile name="io" capacity="8" area="0">
|
||||
<equivalent_sites>
|
||||
<site pb_type="io"/>
|
||||
</equivalent_sites>
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">io.outpad io.inpad</loc>
|
||||
<loc side="top">io.outpad io.inpad</loc>
|
||||
<loc side="right">io.outpad io.inpad</loc>
|
||||
<loc side="bottom">io.outpad io.inpad</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="clb" area="53894">
|
||||
<equivalent_sites>
|
||||
<site pb_type="clb"/>
|
||||
</equivalent_sites>
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<input name="reset" num_pins="1" is_non_clock_global="true"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
|
||||
<fc_override port_name="clk" fc_type="frac" fc_val="0"/>
|
||||
<fc_override port_name="reset" fc_type="frac" fc_val="0"/>
|
||||
</fc>
|
||||
<pinlocations pattern="spread"/>
|
||||
</tile>
|
||||
</tiles>
|
||||
<!-- ODIN II specific config ends -->
|
||||
<!-- Physical descriptions begin -->
|
||||
<layout tileable="true">
|
||||
<auto_layout aspect_ratio="1.0">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</auto_layout>
|
||||
<fixed_layout name="2x2" width="4" height="4">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
<fixed_layout name="4x4" width="6" height="6">
|
||||
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
|
||||
<perimeter type="io" priority="100"/>
|
||||
<corners type="EMPTY" priority="101"/>
|
||||
<!--Fill with 'clb'-->
|
||||
<fill type="clb" priority="10"/>
|
||||
</fixed_layout>
|
||||
</layout>
|
||||
<device>
|
||||
<!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
|
||||
models. We are modifying the delay values however, to include metal C and R, which allows more architecture
|
||||
experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
|
||||
(vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of
|
||||
45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping
|
||||
RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
|
||||
lined up with Stratix IV.
|
||||
We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
|
||||
Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
|
||||
by 2.5x when looking up in Jeff's tables.
|
||||
The delay values are lined up with Stratix IV, which has an architecture similar to this
|
||||
proposed FPGA, and which is also 40 nm
|
||||
C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
|
||||
4x minimum drive strength buffer. -->
|
||||
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
|
||||
<!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
|
||||
area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
|
||||
-->
|
||||
<area grid_logic_tile_area="0"/>
|
||||
<chan_width_distr>
|
||||
<x distr="uniform" peak="1.000000"/>
|
||||
<y distr="uniform" peak="1.000000"/>
|
||||
</chan_width_distr>
|
||||
<switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
|
||||
<connection_block input_switch_name="ipin_cblock"/>
|
||||
</device>
|
||||
<switchlist>
|
||||
<!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
|
||||
book area formula. This means the mux transistors are about 5x minimum drive strength.
|
||||
We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large
|
||||
mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
|
||||
the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
|
||||
by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified
|
||||
buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
|
||||
I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout
|
||||
(diff of second stage) listed below. Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
|
||||
The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by
|
||||
2.5x when looking up in Jeff's tables.
|
||||
Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
|
||||
This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
|
||||
<switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
|
||||
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
|
||||
<switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
|
||||
</switchlist>
|
||||
<segmentlist>
|
||||
<!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.
|
||||
With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
|
||||
reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
|
||||
<!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
|
||||
<segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
|
||||
<mux name="0"/>
|
||||
<sb type="pattern">1 1 1 1 1</sb>
|
||||
<cb type="pattern">1 1 1 1</cb>
|
||||
</segment>
|
||||
</segmentlist>
|
||||
<complexblocklist>
|
||||
<!-- Define I/O pads begin -->
|
||||
<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
|
||||
<!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
|
||||
<pb_type name="io">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
<!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
|
||||
If you need to register the I/O, define clocks in the circuit models
|
||||
These clocks can be handled in back-end
|
||||
-->
|
||||
<!-- A mode denotes the physical implementation of an I/O
|
||||
This mode will be not packable but is mainly used for fabric verilog generation
|
||||
-->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="iopad" blif_model=".subckt io" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="iopad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
|
||||
</direct>
|
||||
<direct name="inpad" input="iopad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
|
||||
<!-- IOs can operate as either inputs or outputs.
|
||||
Delays below come from Ian Kuon. They are small, so they should be interpreted as
|
||||
the delays to and from registers in the I/O (and generally I/Os are registered
|
||||
today and that is when you timing analyze them.
|
||||
-->
|
||||
<mode name="inpad">
|
||||
<pb_type name="inpad" blif_model=".input" num_pb="1">
|
||||
<output name="inpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="inpad" input="inpad.inpad" output="io.inpad">
|
||||
<delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="outpad">
|
||||
<pb_type name="outpad" blif_model=".output" num_pb="1">
|
||||
<input name="outpad" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="outpad" input="io.outpad" output="outpad.outpad">
|
||||
<delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
|
||||
</direct>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- IOs go on the periphery of the FPGA, for consistency,
|
||||
make it physically equivalent on all sides so that only one definition of I/Os is needed.
|
||||
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
|
||||
-->
|
||||
<!-- Place I/Os on the sides of the FPGA -->
|
||||
<power method="ignore"/>
|
||||
</pb_type>
|
||||
<!-- Define I/O pads ends -->
|
||||
<!-- Define general purpose logic block (CLB) begin -->
|
||||
<!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor
|
||||
area is 60 L^2 yields a tile area of 84375 MWTAs.
|
||||
Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area
|
||||
This means that only 37% of our area is in the general routing, and 63% is inside the logic
|
||||
block. Note that the crossbar / local interconnect is considered part of the logic block
|
||||
area in this analysis. That is a lower proportion of of routing area than most academics
|
||||
assume, but note that the total routing area really includes the crossbar, which would push
|
||||
routing area up significantly, we estimate into the ~70% range.
|
||||
-->
|
||||
<pb_type name="clb">
|
||||
<input name="I" num_pins="12" equivalent="full"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="O" num_pins="8" equivalent="none"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Describe fracturable logic element.
|
||||
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
|
||||
The outputs of the fracturable logic element can be optionally registered
|
||||
-->
|
||||
<pb_type name="fle" num_pb="4">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Physical mode definition begin (physical implementation of the fle) -->
|
||||
<mode name="physical" disable_packing="true">
|
||||
<pb_type name="fabric" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="frac_logic" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<output name="lut3_out" num_pins="2"/>
|
||||
<output name="lut4_out" num_pins="1"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
|
||||
<direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
|
||||
<!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
|
||||
<mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<!-- Define flip-flop -->
|
||||
<pb_type name="ff" blif_model=".subckt dffr" num_pb="2">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="ff.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="ff.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="ff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fabric.in" output="frac_logic.in"/>
|
||||
<direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
|
||||
<complete name="direct3" input="fabric.clk" output="ff[1:0].C"/>
|
||||
<complete name="direct4" input="fabric.reset" output="ff[1:0].R"/>
|
||||
<mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
|
||||
</mux>
|
||||
<mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="fabric.in"/>
|
||||
<direct name="direct2" input="fabric.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="fabric.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="fabric.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Physical mode definition end (physical implementation of the fle) -->
|
||||
<!-- Dual 3-LUT mode definition begin -->
|
||||
<mode name="n2_lut3">
|
||||
<pb_type name="lut3inter" num_pb="1">
|
||||
<input name="in" num_pins="3"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="2"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<pb_type name="ble3" num_pb="2">
|
||||
<input name="in" num_pins="3"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define the LUT -->
|
||||
<pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="3" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
|
||||
235e-12
|
||||
235e-12
|
||||
235e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
|
||||
<direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble3.clk" output="ff[0:0].C"/>
|
||||
<direct name="direct4" input="ble3.reset" output="ff[0:0].R"/>
|
||||
<mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
|
||||
<delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
|
||||
<direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
|
||||
<direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
|
||||
<complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
|
||||
<complete name="complete2" input="lut3inter.reset" output="ble3[1:0].reset"/>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
|
||||
<direct name="direct2" input="lut3inter.out" output="fle.out"/>
|
||||
<direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="lut3inter.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- Dual 3-LUT mode definition end -->
|
||||
<!-- 4-LUT mode definition begin -->
|
||||
<mode name="n1_lut4">
|
||||
<!-- Define 4-LUT mode -->
|
||||
<pb_type name="ble4" num_pb="1">
|
||||
<input name="in" num_pins="4"/>
|
||||
<input name="reset" num_pins="1"/>
|
||||
<output name="out" num_pins="1"/>
|
||||
<clock name="clk" num_pins="1"/>
|
||||
<!-- Define LUT -->
|
||||
<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
|
||||
<input name="in" num_pins="4" port_class="lut_in"/>
|
||||
<output name="out" num_pins="1" port_class="lut_out"/>
|
||||
<!-- LUT timing using delay matrix -->
|
||||
<!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
|
||||
we instead take the average of these numbers to get more stable results
|
||||
82e-12
|
||||
173e-12
|
||||
261e-12
|
||||
263e-12
|
||||
398e-12
|
||||
397e-12
|
||||
-->
|
||||
<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
261e-12
|
||||
</delay_matrix>
|
||||
</pb_type>
|
||||
<!-- Define the flip-flop -->
|
||||
<pb_type name="ff" num_pb="1">
|
||||
<input name="D" num_pins="1"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1"/>
|
||||
<clock name="C" num_pins="1"/>
|
||||
<mode name="latch">
|
||||
<pb_type name="latch" blif_model=".latch" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="clk" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="latch.D" clock="clk"/>
|
||||
<T_clock_to_Q max="124e-12" port="latch.Q" clock="clk"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="latch.D"/>
|
||||
<direct name="direct2" input="ff.C" output="latch.clk"/>
|
||||
<direct name="direct3" input="latch.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dff">
|
||||
<pb_type name="dff" blif_model=".subckt dff" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dff.D" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dff.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dff.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dff.C"/>
|
||||
<direct name="direct3" input="dff.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffr">
|
||||
<pb_type name="dffr" blif_model=".subckt dffr" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="R" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffr.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffr.R" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffr.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffr.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffr.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffr.R"/>
|
||||
<direct name="direct4" input="dffr.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<mode name="dffrn">
|
||||
<pb_type name="dffrn" blif_model=".subckt dffrn" num_pb="1">
|
||||
<input name="D" num_pins="1" port_class="D"/>
|
||||
<input name="RN" num_pins="1"/>
|
||||
<output name="Q" num_pins="1" port_class="Q"/>
|
||||
<clock name="C" num_pins="1" port_class="clock"/>
|
||||
<T_setup value="66e-12" port="dffrn.D" clock="C"/>
|
||||
<T_setup value="66e-12" port="dffrn.RN" clock="C"/>
|
||||
<T_clock_to_Q max="124e-12" port="dffrn.Q" clock="C"/>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ff.D" output="dffrn.D"/>
|
||||
<direct name="direct2" input="ff.C" output="dffrn.C"/>
|
||||
<direct name="direct3" input="ff.R" output="dffrn.RN"/>
|
||||
<direct name="direct4" input="dffrn.Q" output="ff.Q"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
|
||||
<direct name="direct2" input="lut4.out" output="ff.D">
|
||||
<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
|
||||
<pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
|
||||
</direct>
|
||||
<direct name="direct3" input="ble4.clk" output="ff.C"/>
|
||||
<direct name="direct4" input="ble4.reset" output="ff.R"/>
|
||||
<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
|
||||
<!-- LUT to output is faster than FF to output on a Stratix IV -->
|
||||
<delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
|
||||
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
|
||||
</mux>
|
||||
</interconnect>
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<direct name="direct1" input="fle.in" output="ble4.in"/>
|
||||
<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
|
||||
<direct name="direct3" input="fle.clk" output="ble4.clk"/>
|
||||
<direct name="direct4" input="fle.reset" output="ble4.reset"/>
|
||||
</interconnect>
|
||||
</mode>
|
||||
<!-- 6-LUT mode definition end -->
|
||||
</pb_type>
|
||||
<interconnect>
|
||||
<!-- We use a full crossbar to get logical equivalence at inputs of CLB
|
||||
The delays below come from Stratix IV. the delay through a connection block
|
||||
input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps
|
||||
delay on the connection block input mux (modeled by Ian Kuon), so the remaining
|
||||
delay within the crossbar is 95 ps.
|
||||
The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
|
||||
Since all our outputs LUT outputs go to a BLE output, and have a delay of
|
||||
25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
|
||||
to get the part that should be marked on the crossbar. -->
|
||||
<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
|
||||
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
|
||||
<delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
|
||||
</complete>
|
||||
<complete name="clks" input="clb.clk" output="fle[3:0].clk">
|
||||
</complete>
|
||||
<complete name="resets" input="clb.reset" output="fle[3:0].reset">
|
||||
</complete>
|
||||
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.
|
||||
By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs,
|
||||
then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
|
||||
naive specification).
|
||||
-->
|
||||
<direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
|
||||
<direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
|
||||
</interconnect>
|
||||
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
|
||||
<!-- Place this general purpose logic block in any unspecified column -->
|
||||
</pb_type>
|
||||
<!-- Define general purpose logic block (CLB) ends -->
|
||||
</complexblocklist>
|
||||
</architecture>
|
||||
|
|
@ -246,8 +246,8 @@
|
|||
<!--pinlocations pattern="spread"/-->
|
||||
<pinlocations pattern="custom">
|
||||
<loc side="left">clb.clk clb.reset clb.set</loc>
|
||||
<loc side="top">clb.cin</loc>
|
||||
<loc side="right">clb.O[9:0] clb.I[19:0]</loc>
|
||||
<loc side="top">clb.cin clb.O[9:0]</loc>
|
||||
<loc side="right">clb.I[19:0]</loc>
|
||||
<loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
|
|
@ -269,8 +269,8 @@
|
|||
<pinlocations pattern="custom">
|
||||
<loc side="left">memory.clk</loc>
|
||||
<loc side="top"></loc>
|
||||
<loc side="right">memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
|
||||
<loc side="bottom">memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
|
||||
<loc side="right">memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
|
||||
<loc side="bottom">memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
|
||||
</pinlocations>
|
||||
</tile>
|
||||
<tile name="mult_18" height="6" area="396000">
|
||||
|
|
|
|||
Loading…
Reference in New Issue