diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys deleted file mode 100644 index e41446605..000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys +++ /dev/null @@ -1,102 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - - -######################### -# Map muxes to pmuxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 5c155b5b9..347359d53 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml @@ -71,4 +71,4 @@ write_analysis_sdc --file ./SDC_analysis exit # Note : -# To run verification at the end of the flow maintain source in ./SRC directory +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga new file mode 100644 index 000000000..506364e30 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION} + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory +{"mode":"full","isActive":false} \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/README.md b/openfpga_flow/openfpga_timing_annotation/README.md new file mode 100644 index 000000000..ae75506db --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/README.md @@ -0,0 +1,28 @@ +Naming convention for timing annotation files +Convention follows the VPR architecture file naming convention, with some extra detail appended to the end. + +k: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. +The keyword 'frac' is to specify if fracturable LUT is used or not. +The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). +N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. +tileable: If the routing architecture is tileable or not. +The keyword 'IO' specifies if the I/O tile is tileable or not +fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable +adder_chain: If hard adder/carry chain is used inside CLBs +register_chain: If shift register chain is used inside CLBs +scan_chain: If scan chain testing infrastructure is used inside CLBs +__mem: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes. +__dsp: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes. +aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os. +multi_io_capacity: If I/O capacity is different on each side of FPGAs. +reduced_io: If I/Os only appear a certain or multiple sides of FPGAs +registerable_io: If I/Os are registerable (can be either combinational or sequential) +: The technology node which the delay numbers are extracted from. +TileOrgz: How tile is organized. +Top-left (Tl): the pins of a tile are placed on the top side and left side only +Top-right (Tr): the pins of a tile are placed on the top side and right side only +Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only +GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks +Other features are used in naming should be listed here. + +tt/ff/ss: timing coners specified at the end of the file name. Each file under the specific architecture is tied to a certain corner, as the timing values will change with the corner. \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml similarity index 76% rename from openfpga_flow/openfpga_timing_annotation/skywater130nm.yml rename to openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml index dd08b1e63..b02721d7a 100644 --- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml @@ -1,33 +1,17 @@ -L1_SB_MUX_DELAY: 1.44e-9 -L2_SB_MUX_DELAY: 1.44e-9 -L4_SB_MUX_DELAY: 1.44e-9 -CB_MUX_DELAY: 1.38e-9 -L1_WIRE_R: 100 -L1_WIRE_C: 1e-12 -L2_WIRE_R: 100 -L2_WIRE_C: 1e-12 -L4_WIRE_R: 100 -L4_WIRE_C: 1e-12 INPAD_DELAY: 0.11e-9 OUTPAD_DELAY: 0.11e-9 FF_T_SETUP: 0.39e-9 FF_T_CLK2Q: 0.43e-9 -LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 -LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 -LUT3_DELAY: 0.92e-9 -LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 LUT4_DELAY: 1.21e-9 LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE -REGIN_TO_FF0_DELAY: 1.12e-9 -FF0_TO_FF1_DELAY: 0.56e-9 CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE @@ -48,15 +32,6 @@ ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 -################# MULT9 Delays ################# - -MULT9_A2Y_DELAY_MAX: 1.523e-9 -MULT9_A2Y_DELAY_MIN: 0.776e-9 -MULT9_B2Y_DELAY_MAX: 1.523e-9 -MULT9_B2Y_DELAY_MIN: 0.776e-9 - - - ################# MULT18 Delays ################# MULT18_A2Y_DELAY_MAX: 1.523e-9 @@ -79,7 +54,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 -DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml new file mode 100644 index 000000000..985f9eb5b --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml @@ -0,0 +1,47 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml new file mode 100644 index 000000000..a2af36f56 --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml @@ -0,0 +1,44 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# MULT18 Delays ################# + +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE +MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt b/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/common/dsp_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/dsp_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/dsp_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_adders_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_adders_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_arith_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_arith_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v new file mode 100644 index 000000000..f8eed8db0 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt new file mode 100644 index 000000000..51617f271 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_128x8 + init 0 + abits 7 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_128x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v new file mode 100644 index 000000000..8cf462c1a --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_128x8 ( + output [0:7] B1DATA, + input CLK1, + input [0:6] B1ADDR, + input [0:6] A1ADDR, + input [0:7] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_128x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v similarity index 94% rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v index 9ec66e6ee..83b44875c 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v @@ -1,58 +1,58 @@ -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) -// Core logic -//----------------------------- -module dpram_128x8_core ( - input wclk, - input wen, - input [0:6] waddr, - input [0:7] data_in, - input rclk, - input ren, - input [0:6] raddr, - output [0:7] data_out ); - - reg [0:7] ram[0:127]; - reg [0:7] internal; - - assign data_out = internal; - - always @(posedge wclk) begin - if(wen) begin - ram[waddr] <= data_in; - end - end - - always @(posedge rclk) begin - if(ren) begin - internal <= ram[raddr]; - end - end - -endmodule - -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) wrapper -// where the read clock and write clock -// are combined to a unified clock -//----------------------------- -module dpram_128x8 ( - input clk, - input wen, - input ren, - input [0:6] waddr, - input [0:6] raddr, - input [0:7] data_in, - output [0:7] data_out ); - - dpram_128x8_core memory_0 ( - .wclk (clk), - .wen (wen), - .waddr (waddr), - .data_in (data_in), - .rclk (clk), - .ren (ren), - .raddr (raddr), - .data_out (data_out) ); - -endmodule +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 5f958e261..57fae9f46 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,13 +7,14 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -run-task benchmark_sweep/counter --debug --show_thread_logs -run-task benchmark_sweep/mac_units --debug --show_thread_logs +# run-task benchmark_sweep/counter --debug --show_thread_logs +# run-task benchmark_sweep/mac_units --debug --show_thread_logs -# Verify MCNC big20 benchmark suite with ModelSim -# Please make sure you have ModelSim installed in the environment -# Otherwise, it will fail -run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# # Verify MCNC big20 benchmark suite with ModelSim +# # Please make sure you have ModelSim installed in the environment +# # Otherwise, it will fail +# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim run-task benchmark_sweep/signal_gen --debug --show_thread_logs +run-task benchmark_sweep/processor --debug --show_thread_logs diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py old mode 100644 new mode 100755 diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index 6caa13456..91c1237fc 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v -yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt -yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 2408323ed..bdbb241e7 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v -yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf new file mode 100644 index 000000000..ea252027f --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf @@ -0,0 +1,39 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout=auto +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v + +[SYNTHESIS_PARAM] +bench0_top = picorv32 +bench0_chan_width = 300 +bench1_top = VexRiscv +bench1_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 9ada9e960..f246a8cf1 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= +openfpga_clock_modeling=ideal openfpga_fast_configuration= [ARCHITECTURES] diff --git a/openfpga_flow/tasks/skywater_openfpga_task b/openfpga_flow/tasks/skywater_openfpga_task deleted file mode 120000 index 4fd397387..000000000 --- a/openfpga_flow/tasks/skywater_openfpga_task +++ /dev/null @@ -1 +0,0 @@ -/home/apond/sofa/SCRIPT/skywater_openfpga_task \ No newline at end of file diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml deleted file mode 100644 index 5351486bc..000000000 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml +++ /dev/null @@ -1,620 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index 2ff83dc49..345be7c8e 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -246,8 +246,8 @@ clb.clk clb.reset clb.set - clb.cin - clb.O[9:0] clb.I[19:0] + clb.cin clb.O[9:0] + clb.I[19:0] clb.cout clb.O[19:10] clb.I[39:20] @@ -269,8 +269,8 @@ memory.clk - memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] - memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4]