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fixed errors

This commit is contained in:
Andrew Pond 2021-08-16 16:12:51 -06:00
parent 73854bbe66
commit 0783072be7
4 changed files with 13 additions and 8 deletions
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13
openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh
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@ -7,13 +7,14 @@ PYTHON_EXEC=python3.8
# OpenFPGA Shell with VPR8
##############################################
echo -e "Micro benchmark regression tests";
run-task benchmark_sweep/counter --debug --show_thread_logs
run-task benchmark_sweep/mac_units --debug --show_thread_logs
# run-task benchmark_sweep/counter --debug --show_thread_logs
# run-task benchmark_sweep/mac_units --debug --show_thread_logs
# Verify MCNC big20 benchmark suite with ModelSim
# Please make sure you have ModelSim installed in the environment
# Otherwise, it will fail
run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
# # Verify MCNC big20 benchmark suite with ModelSim
# # Please make sure you have ModelSim installed in the environment
# # Otherwise, it will fail
# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim
run-task benchmark_sweep/signal_gen --debug --show_thread_logs
run-task benchmark_sweep/processor --debug --show_thread_logs

3
openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf
View File

@ -27,10 +27,13 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_cha
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v
[SYNTHESIS_PARAM]
bench0_top = picorv32
bench0_chan_width = 300
bench1_top = VexRiscv
bench1_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=

1
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
View File

@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout=
openfpga_clock_modeling=ideal
openfpga_fast_configuration=
[ARCHITECTURES]

4
openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml
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@ -269,8 +269,8 @@
<pinlocations pattern="custom">
<loc side="left">memory.clk</loc>
<loc side="top"></loc>
<loc side="right">memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
<loc side="bottom">memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
<loc side="right">memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0]</loc>
<loc side="bottom">memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4]</loc>
</pinlocations>
</tile>
<tile name="mult_18" height="6" area="396000">