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bram timing update

This commit is contained in:
Andrew Pond 2021-07-29 12:32:52 -06:00
parent cb0dbd6f2f
commit 73854bbe66
3 changed files with 3 additions and 3 deletions
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2
openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga
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@ -1,6 +1,6 @@
# Run VPR for the 'and' design
#--write_rr_graph example_rr_graph.xml
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT}
vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT}
# Read OpenFPGA architecture definition
read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

2
openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml
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@ -54,7 +54,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12

2
openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml
View File

@ -37,7 +37,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9
DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9
MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12
MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12