Ganesh Gore
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4f6b8c0905
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Updated regression tests
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2023-02-11 22:11:06 -07:00 |
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Ganesh Gore
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f7c710e95e
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renamed yosys_vpr_template fabric_netlist_gen_template
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2023-02-11 18:33:06 -07:00 |
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Ganesh Gore
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b2bdfb7475
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Strip down task
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2023-02-11 18:32:06 -07:00 |
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Ganesh Gore
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b71a1014e8
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renamed vpr_blif_template to fabric_verification_template
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2023-02-11 18:29:21 -07:00 |
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Ganesh Gore
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6a48f1eb05
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Updated demo projects
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2023-02-11 18:24:20 -07:00 |
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Ganesh Gore
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a6263c44af
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Updated format
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2023-02-11 18:12:04 -07:00 |
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Ganesh Gore
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2afb91596f
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Refactored run_openfpga_task.py
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2023-02-11 18:04:54 -07:00 |
tangxifan
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57cec96d7e
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[script] wrong path to yosys bin
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2023-02-03 22:54:22 -08:00 |
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tangxifan
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ff31a7b828
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[script] fixed the path to yosys bin for openfpga flow
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2023-02-03 22:12:03 -08:00 |
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tangxifan
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aff8178581
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[test] fixed remaining bugs
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2023-01-24 18:00:04 -08:00 |
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tangxifan
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d1e951e52e
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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tangxifan
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f964c9ed67
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[test] debug
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2023-01-24 15:48:57 -08:00 |
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tangxifan
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8174f53796
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[test] deploy new test to fpga bitstream regression
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2023-01-24 15:42:01 -08:00 |
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tangxifan
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499d352cff
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[flow] add yosys rewrite scripts
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2023-01-24 15:39:42 -08:00 |
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tangxifan
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e7a3b48475
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[arch] comment on the wrong mode bits
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2023-01-24 15:24:17 -08:00 |
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tangxifan
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fec84d76d1
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[arch] adding tech lib;
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2023-01-24 15:22:34 -08:00 |
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tangxifan
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1d8c1a6803
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[arch] adding a new arch to validate fracturable dsp
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2023-01-24 15:17:50 -08:00 |
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tangxifan
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d60d0540da
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[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
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tangxifan
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f586229b97
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[test] enable rst_on_lut benchmark
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2023-01-18 19:45:41 -08:00 |
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tangxifan
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b7a66705e0
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[test] now use yosys_vpr flow; add rst_on_lut benchmark
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2023-01-18 19:42:50 -08:00 |
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tangxifan
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bc51be4863
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[benchmark] syntax
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2023-01-18 18:34:24 -08:00 |
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tangxifan
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e974e5ddf7
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[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
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2023-01-18 18:31:36 -08:00 |
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tangxifan
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acc905fa11
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[arch] add support to route reset to LUTs
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2023-01-18 18:22:37 -08:00 |
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tangxifan
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95dd4fd535
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[test] deploy new test to basic regression tests
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2023-01-18 18:17:53 -08:00 |
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tangxifan
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03273371c0
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[test] add a new test to validate local reset
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2023-01-18 18:17:14 -08:00 |
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tangxifan
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c9e00b7abc
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[arch] add a new example arch that supports local reset
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2023-01-18 18:05:52 -08:00 |
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tangxifan
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b6ae829518
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[benchmark] add a new benchmark to validate dff
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2023-01-18 17:59:52 -08:00 |
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tangxifan
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2c9593c1d4
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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tangxifan
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13aed6fff5
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[test] still commment verification out
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2023-01-15 12:17:59 -08:00 |
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tangxifan
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758cc7a089
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[test] debugging
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2023-01-15 11:44:48 -08:00 |
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tangxifan
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14bb76ec87
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[test] remove verification steps for new test but leave a todo
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2023-01-14 23:06:54 -08:00 |
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tangxifan
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297092f1fe
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[arch] now use a local clock as an input of a CLB
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2023-01-14 22:12:00 -08:00 |
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tangxifan
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5aa85d82e6
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[test] deploy the new test to basic regression tests
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2023-01-13 22:07:45 -08:00 |
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tangxifan
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9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
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26f71656de
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[test] update pin constraints
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2023-01-13 21:12:18 -08:00 |
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tangxifan
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9e462d96e0
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[arch] now use a dedicated input for locally generated clock signals
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2023-01-13 20:46:04 -08:00 |
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tangxifan
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93107c752a
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[test] updating test case
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2023-01-13 19:53:15 -08:00 |
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tangxifan
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1fb39f803b
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[doc] updated vpr arch naming rules
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2023-01-13 19:52:58 -08:00 |
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tangxifan
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a06ee30ca0
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[arch] added a new vpr arch where clock can be generated by internal logics
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2023-01-13 19:35:00 -08:00 |
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tangxifan
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1353577351
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[test] added a new test to validate locally generated clocks
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2023-01-13 16:45:30 -08:00 |
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tangxifan
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6400605603
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[benchmark] add clock divider
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2023-01-13 16:39:06 -08:00 |
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tangxifan
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bbf83101be
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[test] deploy new test to ci
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2023-01-11 17:11:28 -08:00 |
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tangxifan
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c7dc3ce7dc
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[test] pass
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2023-01-11 17:10:29 -08:00 |
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tangxifan
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f6f153ace4
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[test] debugging
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2023-01-11 17:06:31 -08:00 |
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tangxifan
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d5ebbeea9a
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[test] adding a new test to show how to automate generation of bus group files
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2023-01-11 16:59:54 -08:00 |
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tangxifan
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54c3b965f2
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[script] fixed a bug
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2023-01-01 17:19:11 -08:00 |
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tangxifan
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3c8e157d7b
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[script] rename and fix typo
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2023-01-01 17:13:23 -08:00 |
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tangxifan
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43cb498827
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[test] deploy new tests to basic regression tests
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2023-01-01 17:07:25 -08:00 |
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tangxifan
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83d7ff56e1
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[script] add dedicated testcase for source commands
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2023-01-01 17:04:24 -08:00 |
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tangxifan
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cdec0cf28c
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[script] add a custom variable to specify the path to openfpga shell script
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2023-01-01 16:51:21 -08:00 |