tangxifan
|
afe8278670
|
put routing module builder online
|
2020-02-13 17:35:29 -07:00 |
|
tangxifan
|
cf440f92d3
|
put routing module builder util function online
|
2020-02-13 16:05:23 -07:00 |
|
tangxifan
|
89086ed080
|
add verbose output to build grid module
|
2020-02-13 15:38:26 -07:00 |
|
tangxifan
|
072965cd64
|
make grid module builder online; basic support on physical tiles
|
2020-02-13 15:27:16 -07:00 |
|
tangxifan
|
578d7eb824
|
Merge branch 'refactoring' into dev
|
2020-02-12 20:49:55 -07:00 |
|
tangxifan
|
59d579425e
|
add utils for duplicate pins in grid module builder
|
2020-02-12 20:48:07 -07:00 |
|
tangxifan
|
895d5b5a0a
|
add utils for grid module builder
|
2020-02-12 20:25:05 -07:00 |
|
tangxifan
|
002c2795fe
|
add memory module builder
|
2020-02-12 20:06:38 -07:00 |
|
tangxifan
|
8e381f0581
|
add wire module builder
|
2020-02-12 19:57:15 -07:00 |
|
tangxifan
|
e842150cc5
|
add lut module builder
|
2020-02-12 19:52:41 -07:00 |
|
tangxifan
|
fddd3c9463
|
add mux module builder
|
2020-02-12 19:45:14 -07:00 |
|
tangxifan
|
ea7d879b4f
|
add decoder module builder
|
2020-02-12 18:28:50 -07:00 |
|
tangxifan
|
6ca9eb0056
|
Merge branch 'refactoring' into dev
|
2020-02-12 17:54:10 -07:00 |
|
tangxifan
|
f11832b8cf
|
start integrating module graph builder
|
2020-02-12 17:53:23 -07:00 |
|
tangxifan
|
13fadd0f91
|
move compact routing hierarchy to build_fabric command
|
2020-02-12 15:49:47 -07:00 |
|
tangxifan
|
df3ae60954
|
add default configurable memory model set-up when reading openfpga architecture XML
|
2020-02-12 15:19:40 -07:00 |
|
tangxifan
|
c78d3e9af1
|
add mux library builder
|
2020-02-12 14:58:23 -07:00 |
|
tangxifan
|
ce63b1cc62
|
add circuit model binding for direct connections and enhance model type checking
|
2020-02-12 11:40:20 -07:00 |
|
tangxifan
|
4a05cec037
|
add rr_segment binding to circuit model
|
2020-02-12 11:21:40 -07:00 |
|
tangxifan
|
a736e09c29
|
add rr_switch binding in link openfpga arch command
|
2020-02-12 10:52:20 -07:00 |
|
tangxifan
|
feccbc5780
|
add more methods to link routing to circuit models in device annotation
|
2020-02-12 10:08:54 -07:00 |
|
tangxifan
|
a31d6c6d1e
|
rename pb_type annotation to device annotation
|
2020-02-12 09:52:18 -07:00 |
|
tangxifan
|
4367dba9b7
|
move mux graph and decoder builders to vpr8 integration; ready to link the rr_switch to circuit models
|
2020-02-11 21:02:58 -07:00 |
|
tangxifan
|
175bef014a
|
add compact_routing hierarchy command
|
2020-02-11 17:40:37 -07:00 |
|
tangxifan
|
1372f748f1
|
put GSB builder online
|
2020-02-11 16:37:14 -07:00 |
|
tangxifan
|
e2e115e6f3
|
improve rr_node fast look-up in rr_graph object so that we have easily find all the channel nodes
|
2020-02-11 11:33:30 -07:00 |
|
tangxifan
|
85f3826939
|
put device rr_gsb online. Ready to plug-in
|
2020-02-09 14:58:23 -07:00 |
|
tangxifan
|
230c7b709a
|
put rr_gsb data structure online
|
2020-02-09 00:20:44 -07:00 |
|
tangxifan
|
0b6b3bc029
|
start adapting rr_gsb related data structure
|
2020-02-07 11:32:33 -07:00 |
|
tangxifan
|
3d7eff64b9
|
bug fixed for lut truth table fixup. Results look good
|
2020-02-06 17:47:25 -07:00 |
|
tangxifan
|
ed9e038845
|
add functionality of LUT truth table fix-up
|
2020-02-06 17:14:29 -07:00 |
|
tangxifan
|
99f5a86b49
|
bug fixed for routing annotation and routing net fix-up
|
2020-02-06 12:54:55 -07:00 |
|
tangxifan
|
cccbb9fd49
|
add missing files
|
2020-02-05 22:12:44 -07:00 |
|
tangxifan
|
dad204674b
|
done an initial version of clustering net fix-up based on routing results. Debugging on the way
|
2020-02-05 21:50:52 -07:00 |
|
tangxifan
|
6dc2126ce6
|
Merge branch 'refactoring' into dev
|
2020-02-04 22:54:19 -07:00 |
|
tangxifan
|
e89d8e4493
|
bug fix for clock connection builder by supporting fake switch when adding edges to RRGraph object
|
2020-02-04 21:56:54 -07:00 |
|
tangxifan
|
7092ddbde6
|
bug fix for root node builder by including ptc_num!!
|
2020-02-04 21:54:03 -07:00 |
|
tangxifan
|
e2f408cc2d
|
bug fix for clock network builder using rr_graph object
|
2020-02-04 21:32:05 -07:00 |
|
tangxifan
|
ecc3b8a4f0
|
bug fix in router lookhead map when find rr_graph nodes
|
2020-02-04 21:02:55 -07:00 |
|
tangxifan
|
a3a85bf259
|
bug fix for direct connections in rr_graph builder
|
2020-02-04 20:45:14 -07:00 |
|
tangxifan
|
0cce1f4efc
|
bug fixing for heterogenenous FPGA when using the RRGraph object
|
2020-02-04 17:31:39 -07:00 |
|
tangxifan
|
f098d40af1
|
correct missing rr_nodes usage to rr_graph obj
|
2020-02-04 16:48:15 -07:00 |
|
tangxifan
|
e3db937daa
|
fixed routing stats
|
2020-02-04 16:20:25 -07:00 |
|
tangxifan
|
969dd7c467
|
rr_graph working
|
2020-02-04 15:33:15 -07:00 |
|
tangxifan
|
6881863506
|
keep debugging rr_graph builder
|
2020-02-04 15:21:45 -07:00 |
|
tangxifan
|
15167c9bfb
|
bug fixing for building routing channels in build_rr_graph()
|
2020-02-04 11:37:59 -07:00 |
|
tangxifan
|
b6a2013565
|
minor bug fix for RRGraph data structure
|
2020-02-03 21:50:02 -07:00 |
|
tangxifan
|
6bd71f198e
|
keep debugging the rr_graph generator. Definitely should rework the RREdge creation functions
|
2020-02-03 21:05:50 -07:00 |
|
tangxifan
|
898ed891d2
|
midway in debugging the refactored rr_graph builder
|
2020-02-03 19:05:18 -07:00 |
|
tangxifan
|
9f3afb5a46
|
refactored rr_graph clock builder
|
2020-02-03 15:11:24 -07:00 |