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refactored rr_graph clock builder

This commit is contained in:
tangxifan 2020-02-03 15:11:24 -07:00
parent fc6389b5c0
commit 9f3afb5a46
6 changed files with 53 additions and 46 deletions
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2
vpr/src/route/clock_connection_builders.cpp
View File

@ -137,7 +137,7 @@ void ClockToClockConneciton::set_fc_val(float fc_val) {
void ClockToClockConneciton::create_switches(const ClockRRGraphBuilder& clock_graph) {
auto& device_ctx = g_vpr_ctx.mutable_device();
auto& grid = device_ctx.grid;
auto& rr_nodes = device_ctx.rr_nodes;
auto& rr_graph = device_ctx.rr_graph;
auto to_locations = clock_graph.get_switch_locations(to_clock, to_switch);

45
vpr/src/route/clock_network_builders.cpp
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@ -180,7 +180,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
(void)num_segments;
auto& device_ctx = g_vpr_ctx.mutable_device();
auto& rr_nodes = device_ctx.rr_nodes;
auto& rr_graph = device_ctx.rr_graph;
auto& grid = device_ctx.grid;
int ptc_num = clock_graph.get_and_increment_chanx_ptc_num(); // used for drawing
@ -231,7 +231,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
y,
ptc_num,
BI_DIRECTION,
rr_nodes);
rr_graph);
clock_graph.add_switch_location(get_name(), drive.name, drive_x, y, drive_node_idx);
// create rib wire to the right and left of the drive point
@ -240,13 +240,13 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
y,
ptc_num,
DEC_DIRECTION,
rr_nodes);
rr_graph);
auto right_node_idx = create_chanx_wire(drive_x + 1,
x_end,
y,
ptc_num,
INC_DIRECTION,
rr_nodes);
rr_graph);
record_tap_locations(x_start + x_offset,
x_end,
y,
@ -255,28 +255,27 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
clock_graph);
// connect drive point to each half rib using a directed switch
rr_nodes[drive_node_idx].add_edge(left_node_idx, drive.switch_idx);
rr_nodes[drive_node_idx].add_edge(right_node_idx, drive.switch_idx);
rr_graph.create_edge(drive_node_idx, left_node_idx, drive.switch_idx);
rr_graph.create_edge(drive_node_idx, right_node_idx, drive.switch_idx);
}
}
}
int ClockRib::create_chanx_wire(int x_start,
int x_end,
int y,
int ptc_num,
e_direction direction,
std::vector<t_rr_node>& rr_nodes) {
rr_nodes.emplace_back();
auto node_index = rr_nodes.size() - 1;
RRNodeId ClockRib::create_chanx_wire(int x_start,
int x_end,
int y,
int ptc_num,
e_direction direction,
RRGraph& rr_graph) {
RRNodeId node_index rr_graph.create_node(CHANX);
rr_nodes[node_index].set_coordinates(x_start, y, x_end, y);
rr_nodes[node_index].set_type(CHANX);
rr_nodes[node_index].set_capacity(1);
rr_nodes[node_index].set_track_num(ptc_num);
rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(
rr_graph.set_node_bounding_box(node_index, vtr::Rect<size_t>(x_start, y, x_end, y));
rr_graph.set_node_type(node_index, CHANX);
rr_graph.set_node_capacity(node_index, 1);
rr_graph.set_node_track_num(node_index, ptc_num);
rr_graph.set_node_rc_index(node_index, find_create_rr_rc_data(
x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal));
rr_nodes[node_index].set_direction(direction);
rr_graph.set_node_direction(node_index, direction);
short seg_index = 0;
switch (direction) {
@ -293,7 +292,7 @@ int ClockRib::create_chanx_wire(int x_start,
VTR_ASSERT_MSG(false, "Unidentified direction type for clock rib");
break;
}
rr_nodes[node_index].set_cost_index(CHANX_COST_INDEX_START + seg_index); // Actual value set later
rr_graph.set_node_cost_index(node_index, CHANX_COST_INDEX_START + seg_index); // Actual value set later
return node_index;
}
@ -301,8 +300,8 @@ int ClockRib::create_chanx_wire(int x_start,
void ClockRib::record_tap_locations(unsigned x_start,
unsigned x_end,
unsigned y,
int left_rr_node_idx,
int right_rr_node_idx,
const RRNodeId& left_rr_node_idx,
const RRNodeId& right_rr_node_idx,
ClockRRGraphBuilder& clock_graph) {
for (unsigned x = x_start + tap.offset; x <= x_end; x += tap.increment) {
if (x < (x_start + drive.offset - 1)) {

10
vpr/src/route/rr_graph.cpp
View File

@ -377,7 +377,7 @@ void create_rr_graph(const t_graph_type graph_type,
}
/* Xifan Tang - Create rr_graph object: load rr_nodes to the object */
convert_rr_graph(segment_inf);
//convert_rr_graph(segment_inf);
}
process_non_config_sets();
@ -597,6 +597,14 @@ static void build_rr_graph(const t_graph_type graph_type,
device_ctx.rr_graph = alloc_and_load_rr_node_indices(max_chan_width, grid,
&num_rr_nodes, chan_details_x, chan_details_y);
/* The number of segments are in general small, reserve segments may not bring
* significant memory efficiency */
device_ctx.rr_graph.reserve_segments(segment_inf.size());
// Create the segments
for (size_t iseg = 0; iseg < segment_inf.size(); ++iseg) {
device_ctx.rr_graph.create_segment(segment_inf[iseg]);
}
/* These are data structures used by the the unidir opin mapping. They are used
* to spread connections evenly for each segment type among the available
* wire start points */

32
vpr/src/route/rr_graph_clock.cpp
View File

@ -24,22 +24,20 @@ void ClockRRGraphBuilder::create_and_append_clock_rr_graph(std::vector<t_segment
auto& clock_networks = device_ctx.clock_networks;
auto& clock_routing = device_ctx.clock_connections;
size_t clock_nodes_start_idx = device_ctx.rr_nodes.size();
size_t clock_nodes_start_idx = device_ctx.rr_graph.nodes().size();
ClockRRGraphBuilder clock_graph = ClockRRGraphBuilder();
clock_graph.create_clock_networks_wires(clock_networks, segment_inf.size());
clock_graph.create_clock_networks_switches(clock_routing);
// Reset fanin to account for newly added clock rr_nodes
init_fan_in(device_ctx.rr_nodes, device_ctx.rr_nodes.size());
clock_graph.add_rr_switches_and_map_to_nodes(clock_nodes_start_idx, R_minW_nmos, R_minW_pmos);
// "Partition the rr graph edges for efficient access to configurable/non-configurable
// edge subsets. Must be done after RR switches have been allocated"
partition_rr_graph_edges(device_ctx);
device_ctx.rr_graph.rebuild_node_edges();
alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_node_indices,
alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
chan_width->max, wire_to_rr_ipin_switch, base_cost_type);
float elapsed_time = (float)(clock() - begin) / CLOCKS_PER_SEC;
@ -55,8 +53,8 @@ void ClockRRGraphBuilder::create_clock_networks_wires(std::vector<std::unique_pt
}
// Reduce the capacity of rr_nodes for performance
auto& rr_nodes = g_vpr_ctx.mutable_device().rr_nodes;
rr_nodes.shrink_to_fit();
auto& rr_graph = g_vpr_ctx.mutable_device().rr_graph;
rr_graph.compress();
}
// Clock switch information comes from the arch file
@ -70,18 +68,18 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
const float R_minW_nmos,
const float R_minW_pmos) {
auto& device_ctx = g_vpr_ctx.mutable_device();
auto& rr_nodes = device_ctx.rr_nodes;
auto& rr_graph = device_ctx.rr_graph;
// Check to see that clock nodes were sucessfully appended to rr_nodes
VTR_ASSERT(rr_nodes.size() > node_start_idx);
VTR_ASSERT(true == rr_graph.valid_node_id(RRNodeId(node_start_idx));
std::unordered_map<int, int> arch_switch_to_rr_switch;
// The following assumes that arch_switch was specified earlier when the edges where added
for (size_t node_idx = node_start_idx; node_idx < rr_nodes.size(); node_idx++) {
auto& from_node = rr_nodes[node_idx];
for (t_edge_size edge_idx = 0; edge_idx < from_node.num_edges(); edge_idx++) {
int arch_switch_idx = from_node.edge_switch(edge_idx);
for (size_t node_idx = node_start_idx; node_idx < rr_graph.nodes().size(); node_idx++) {
const RRNodeId& from_node = RRNodeId(node_idx);
for (const RREdgeId& edge_idx : rr_graph.node_out_edges(from_node)) {
int arch_switch_idx = rr_graph.edge_switch(edge_idx);
int rr_switch_idx;
auto itter = arch_switch_to_rr_switch.find(arch_switch_idx);
@ -94,7 +92,7 @@ void ClockRRGraphBuilder::add_rr_switches_and_map_to_nodes(size_t node_start_idx
rr_switch_idx = itter->second;
}
from_node.set_edge_switch(edge_idx, rr_switch_idx);
rr_graph.set_edge_switch(edge_idx, rr_switch_idx);
}
}
@ -125,17 +123,17 @@ void ClockRRGraphBuilder::add_switch_location(std::string clock_name,
std::string switch_point_name,
int x,
int y,
int node_index) {
const RRNodeId& node_index) {
// Note use of operator[] will automatically insert clock name if it doesn't exist
clock_name_to_switch_points[clock_name].insert_switch_node_idx(switch_point_name, x, y, node_index);
}
void SwitchPoints::insert_switch_node_idx(std::string switch_point_name, int x, int y, int node_idx) {
void SwitchPoints::insert_switch_node_idx(std::string switch_point_name, int x, int y, const RRNodeId& node_idx) {
// Note use of operator[] will automatically insert switch name if it doesn't exit
switch_point_name_to_switch_location[switch_point_name].insert_node_idx(x, y, node_idx);
}
void SwitchPoint::insert_node_idx(int x, int y, int node_idx) {
void SwitchPoint::insert_node_idx(int x, int y, const RRNodeId& node_idx) {
// allocate 2d vector of grid size
if (rr_node_indices.empty()) {
auto& grid = g_vpr_ctx.device().grid;

4
vpr/src/route/rr_graph_clock.h
View File

@ -13,6 +13,8 @@
#include "clock_network_builders.h"
#include "clock_connection_builders.h"
#include "rr_graph_obj_fwd.h"
class ClockNetwork;
class ClockConnection;
@ -23,7 +25,7 @@ class SwitchPoint {
* Examples of SwitchPoint(s) are rib-to-spine, driver-to-spine. */
public:
// [grid_width][grid_height][0..nodes_at_this_location-1]
std::vector<std::vector<std::vector<int>>> rr_node_indices;
std::vector<std::vector<std::vector<RRNodeId>>> rr_node_indices;
// Set of all the locations for this switch point. Used to quickly find
// if the switch point exists at a certian location.
std::set<std::pair<int, int>> locations; // x,y

6
vpr/src/route/rr_graph_reader.cpp
View File

@ -281,17 +281,17 @@ void process_seg_id(pugi::xml_node parent, const pugiutil::loc_data& loc_data) {
while (rr_node) {
id = get_attribute(rr_node, "id", loc_data).as_int();
auto& node = device_ctx.rr_nodes[id];
auto& node = RRNodeId(id);
segmentSubnode = get_single_child(rr_node, "segment", loc_data, pugiutil::OPTIONAL);
if (segmentSubnode) {
attribute = get_attribute(segmentSubnode, "segment_id", loc_data, pugiutil::OPTIONAL);
if (attribute) {
int seg_id = get_attribute(segmentSubnode, "segment_id", loc_data).as_int(0);
device_ctx.rr_indexed_data[node.cost_index()].seg_index = seg_id;
device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = seg_id;
} else {
//-1 for non chanx or chany nodes
device_ctx.rr_indexed_data[node.cost_index()].seg_index = -1;
device_ctx.rr_indexed_data[device_ctx.rr_graph.node_cost_index(node)].seg_index = -1;
}
}
rr_node = rr_node.next_sibling(rr_node.name());