tangxifan
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5ccb4adb08
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refactored LB router main function
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2020-02-19 11:09:24 -07:00 |
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tangxifan
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3d5a15d41e
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refactored most functions except echo and try_route() in LbRouter
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2020-02-19 00:07:36 -07:00 |
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tangxifan
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80fa6f8a0a
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refactored skip nets in LbRouter
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2020-02-18 22:08:51 -07:00 |
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tangxifan
|
289c869caf
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refactored expand rt_node in LbRouter
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2020-02-18 22:01:22 -07:00 |
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tangxifan
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c7ef14fc23
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refactoring node expansion in LbRouter
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2020-02-18 21:51:03 -07:00 |
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tangxifan
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11879d43b4
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add methods one by one to LbRouter from cluster_router.cpp
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2020-02-18 19:22:36 -07:00 |
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tangxifan
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0310dafe42
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add accessors to LBRouter
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2020-02-18 18:35:00 -07:00 |
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tangxifan
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1799db810d
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compilation error fix
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2020-02-18 17:04:36 -07:00 |
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tangxifan
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d58d14df8e
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start encapsulate the whole lb router in an object
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2020-02-18 16:50:56 -07:00 |
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tangxifan
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ed25ccc70f
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start refactoring lb router in openfpga namespace
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2020-02-18 12:00:27 -07:00 |
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tangxifan
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ef11482a95
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fix dependency error in pack_types header file
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2020-02-18 11:36:16 -07:00 |
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tangxifan
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098f7dddf3
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Merge branch 'refactoring' into dev
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2020-02-18 11:04:22 -07:00 |
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tangxifan
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6060440b97
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fine tuning for the verbose output
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2020-02-17 21:14:15 -07:00 |
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tangxifan
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409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
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8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
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62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
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6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
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92076c1460
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refactored lb_rr_graph in the same principle of RRGraph object
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2020-02-17 16:59:24 -07:00 |
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tangxifan
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95accb662b
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Merge branch 'refactoring' into dev
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2020-02-16 16:36:20 -07:00 |
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tangxifan
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60f40a9657
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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tangxifan
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11775c370b
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |
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tangxifan
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e37ac8a098
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add grid module Verilog writer
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2020-02-16 16:04:41 -07:00 |
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tangxifan
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c20caa1fa3
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routing module Verilog writer is online
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2020-02-16 14:47:54 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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99c3712b6f
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adapt Verilog wire module writer
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2020-02-16 12:59:37 -07:00 |
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tangxifan
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5cc68b0730
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adapt LUT Verilog writer
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2020-02-16 12:45:58 -07:00 |
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tangxifan
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105ccabecc
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adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
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a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
|
3efd1a2a6d
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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tangxifan
|
cf34339e96
|
adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |
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tangxifan
|
2eba882332
|
put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
|
2035afc34b
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Merge branch 'refactoring' into dev
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2020-02-16 00:04:29 -07:00 |
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tangxifan
|
4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
|
0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |
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tangxifan
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bf54be3d00
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add option data structure for FPGA Verilog
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2020-02-15 21:39:47 -07:00 |
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tangxifan
|
da79ef687c
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add missing files
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2020-02-15 20:54:37 -07:00 |
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tangxifan
|
8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |
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tangxifan
|
622c7826d1
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start transplanting fpga_verilog
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2020-02-15 15:03:00 -07:00 |
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tangxifan
|
45914e8afa
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Merge branch 'refactoring' into dev
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2020-02-15 14:14:54 -07:00 |
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tangxifan
|
85627dc128
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put build top module online
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2020-02-15 14:13:32 -07:00 |
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tangxifan
|
539f13720a
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tile direct supports inter-column/inter-row direct connections
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2020-02-15 13:42:53 -07:00 |
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tangxifan
|
ee8f5542e9
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Merge branch 'refactoring' into dev
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2020-02-14 22:22:04 -07:00 |
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tangxifan
|
213c611c0b
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add tile direct builder
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2020-02-14 22:21:32 -07:00 |
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tangxifan
|
7e86cf1079
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add tile direct data structure
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2020-02-14 19:11:49 -07:00 |
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tangxifan
|
59c13550e0
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add direct annotation with inter-column/row syntax
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2020-02-14 17:40:59 -07:00 |
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tangxifan
|
c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |
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tangxifan
|
9dc9c2c9f7
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add build top module connection functions
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2020-02-14 10:45:24 -07:00 |
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tangxifan
|
36179b6ced
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start moving top-module builder. Now adapt the utils
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2020-02-14 10:00:24 -07:00 |
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tangxifan
|
a6fd0257aa
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Merge branch 'refactoring' into dev
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2020-02-13 17:36:10 -07:00 |