tangxifan
|
aef94171c2
|
[doc] update options for pcf2place command
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2022-10-17 13:55:18 -07:00 |
|
tangxifan
|
58487c7766
|
[doc] add more notes about the commmand ``pb_pin_fixup``
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2022-09-29 11:01:07 -07:00 |
|
tangxifan
|
9b65472ffb
|
[doc] update compilation guidelines
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2022-09-26 16:22:40 -07:00 |
|
tangxifan
|
48f776d49b
|
[doc] update documentation about the new option
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2022-09-12 16:58:32 -07:00 |
|
tangxifan
|
0609210b39
|
[doc] update doc with the new xml syntax
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2022-09-08 17:00:16 -07:00 |
|
tangxifan
|
50813d90a2
|
[doc] update documentation based on the actual implementation on rr_gsb writer
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2022-08-29 20:45:31 -07:00 |
|
tangxifan
|
12a30196e0
|
[engine] updating gsb writer; Unfinished!!!
|
2022-08-29 16:58:48 -07:00 |
|
tangxifan
|
adbc69f081
|
[doc] add new options for GSB writer
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2022-08-29 14:16:51 -07:00 |
|
tangxifan
|
77abb86dab
|
[doc] update documentation about the activity file options
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2022-08-01 21:37:22 -07:00 |
|
tangxifan
|
84dbcd61dd
|
[doc] fixed a few typo and format errors
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2022-07-28 19:09:53 -07:00 |
|
tangxifan
|
c16bcd7f63
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[doc] add file formates required by pcf2place
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2022-07-28 16:35:13 -07:00 |
|
tangxifan
|
860591ff3f
|
[doc] add pcf file format to documentation
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2022-07-28 16:15:44 -07:00 |
|
tangxifan
|
6e5fde56ce
|
[doc] add pcf2place to command list
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2022-07-28 16:06:57 -07:00 |
|
tangxifan
|
2b4beb632c
|
[doc] fix a bug in including io information file format
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2022-07-26 15:50:35 -07:00 |
|
tangxifan
|
bf2b1da801
|
[doc] add the new command file format to documentation
|
2022-07-26 14:06:07 -07:00 |
|
tangxifan
|
21a0415ff3
|
Update compile.rst
|
2022-07-21 17:52:21 -07:00 |
|
tangxifan
|
929c74b3b0
|
Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into hotfix_reg
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2022-05-23 09:11:18 +08:00 |
|
tangxifan
|
7a0f796b7c
|
[doc] add missing file link and show version number in frontpage README
|
2022-05-22 15:27:22 +08:00 |
|
tangxifan
|
78313b3593
|
[Misc] Now version number is in a separated file; Cmakefile and doc read the file and build version number on fly; CI can also update version
|
2022-05-22 15:22:43 +08:00 |
|
tangxifan
|
1794578b49
|
[doc] code format
|
2022-05-22 14:04:12 +08:00 |
|
tangxifan
|
07df4611e8
|
[doc] more tips
|
2022-05-22 13:46:13 +08:00 |
|
tangxifan
|
61a1462c21
|
[doc] add guidelines about running regression tests
|
2022-05-22 13:44:48 +08:00 |
Ganesh Gore
|
daae02a614
|
Minor documentation update
|
2022-05-08 13:03:16 -06:00 |
|
Ganesh Gore
|
1e243650b9
|
Added option to copy example projects
|
2022-05-03 14:06:16 -06:00 |
|
Ganesh Gore
|
42567d8178
|
Updated docuementation
|
2022-05-02 12:56:31 -06:00 |
|
tangxifan
|
907308ee0f
|
[Doc] Update bitstream distribution file format
|
2022-03-29 20:09:24 +08:00 |
taoli4rs
|
781250f0bb
|
Fix a small typo to trigger the CI flow.
|
2022-03-22 16:36:45 -07:00 |
|
tangxifan
|
6ff69d26b9
|
[Doc] An example to the documentation about the new feature in tile_annotation
|
2022-03-20 13:12:13 +08:00 |
|
tangxifan
|
123bb70cb3
|
[Doc] More explanantion on the use of config_enable attribute for circuit ports
|
2022-02-23 15:53:58 -08:00 |
|
tangxifan
|
b78e58d9bf
|
[Doc] Update doc about big endian syntax in bus group file format
|
2022-02-18 23:07:18 -08:00 |
|
tangxifan
|
8116141210
|
[Doc] Update documentation on the bus group feature
|
2022-02-18 15:46:25 -08:00 |
|
tangxifan
|
37d8617a5c
|
[Doc] Update due to new options
|
2022-02-17 19:45:37 -08:00 |
|
tangxifan
|
4a78bcf5d3
|
[Doc] update file format about bus group
|
2022-02-17 15:15:05 -08:00 |
|
tangxifan
|
f5e0d685cf
|
[Doc] Adjust figure width
|
2022-02-17 14:29:09 -08:00 |
|
tangxifan
|
796428d848
|
[Doc] Add documentation about bus group file format
|
2022-02-17 14:22:21 -08:00 |
|
tangxifan
|
2b5fded2a9
|
[Doc] Update documentation on the new option
|
2022-02-01 13:25:58 -08:00 |
|
tangxifan
|
b7b0a2a5d8
|
[Doc] Update doc about the new option
|
2022-02-01 12:19:26 -08:00 |
|
tangxifan
|
63f44adf15
|
[FPGA-Verilog] Now have a new option ``--use_relative_path``
|
2022-01-31 12:48:05 -08:00 |
|
tangxifan
|
a9a56686e2
|
[Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml``
|
2022-01-26 11:10:29 -08:00 |
|
tangxifan
|
25143d07f1
|
[FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files
|
2022-01-25 13:37:54 -08:00 |
|
tangxifan
|
a4659020f2
|
Merge branch 'master' into time_stamp
|
2022-01-25 12:11:35 -08:00 |
|
tangxifan
|
62b57b05d2
|
[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``
|
2022-01-25 12:09:08 -08:00 |
Aram Kostanyan
|
758453f725
|
Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
|
2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
|
bd158311c5
|
Fixed typo in documentation and updated 'benchmark_sweep/iwls2005' task to use list of HDL files for 'iwls2005/ethernet' benchmark.
|
2022-01-18 14:07:41 +05:00 |
|
Aram Kostanyan
|
588ee14920
|
Merge branch 'master' into issue-483
|
2022-01-18 13:38:12 +05:00 |
|
Aram Kostanyan
|
fb2e4377c8
|
Added missing changes from previous commit.
|
2022-01-17 19:42:40 +05:00 |
|
Aram Kostanyan
|
2b008177e7
|
Updated documentation.
|
2022-01-17 14:58:20 +05:00 |
Awais Abbas
|
54d4f30592
|
OpenFPGA Documentation updated for yosys only support
|
2022-01-14 16:14:48 +05:00 |
|
tangxifan
|
80c6d5887d
|
Merge branch 'ql_mem_bank_opensource' of https://github.com/RapidSilicon/OpenFPGA_RS into ql_mem_bank
|
2021-12-29 10:57:46 -08:00 |
|
tangxifan
|
b2ba0d0c42
|
[Doc] Add version naming convention to developer guidelines
|
2021-12-22 15:12:14 -08:00 |
nadeemyaseen-rs
|
236910cde4
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-12-09 00:00:21 +05:00 |
|
tangxifan
|
1e5afb985c
|
Update contact.rst
|
2021-11-30 20:25:15 -08:00 |
|
nadeemyaseen-rs
|
1ea56b2d18
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-11-18 00:00:55 +05:00 |
|
Aram Kostanyan
|
a355977420
|
Adding Yosys+Verific support.
|
2021-10-29 18:34:27 +05:00 |
|
tangxifan
|
b8d5920529
|
Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
|
2021-10-28 15:45:58 -07:00 |
|
Ganesh Gore
|
130805d50c
|
Updated CI documentation
|
2021-10-21 15:17:30 -06:00 |
|
nadeemyaseen-rs
|
e0cfd46ec7
|
Merge remote-tracking branch 'upstream/master' into update_from_upstream
|
2021-10-14 19:25:31 +05:00 |
|
tangxifan
|
57159fc121
|
[Doc] Update documentation for the new syntax in configuration protocol and fabric key file format
|
2021-10-10 17:46:45 -07:00 |
|
tangxifan
|
40b589dc6d
|
[Doc] Update documentation about the clock definition for programming clocks in simulation settings
|
2021-10-06 13:50:33 -07:00 |
|
tangxifan
|
03bcf6dee5
|
[Doc] Update documenation for the new option ``--keep_dont_care_bits``
|
2021-10-05 19:23:42 -07:00 |
|
tangxifan
|
ff339312f6
|
[Doc] Update documentation about the limitations of multi-region configuration protocols
|
2021-10-05 11:55:10 -07:00 |
|
tangxifan
|
9a7e0f761a
|
[Doc] Add fabric bitstream file format for QL memory bank
|
2021-10-04 12:29:49 -07:00 |
|
tangxifan
|
a01fa7c282
|
[Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank
|
2021-10-04 12:09:42 -07:00 |
|
tangxifan
|
b0a97a7052
|
[Doc] Update doc about WLR usage for QL memory bank
|
2021-09-27 10:24:04 -07:00 |
|
tangxifan
|
f9bceff33a
|
[Doc] Update documentation for the flatten BL/WL protocols
|
2021-09-25 20:44:45 -07:00 |
|
tangxifan
|
10774dc15c
|
[Doc] Updated documentation about new syntax in fabric key
|
2021-09-21 17:01:52 -07:00 |
|
tangxifan
|
d9d959709c
|
[Doc] Add missing figures
|
2021-09-20 20:31:53 -07:00 |
|
tangxifan
|
3146d2484f
|
[Doc] Update documentation on the WLR definition for circuit model
|
2021-09-20 17:21:33 -07:00 |
|
tangxifan
|
73d21c9730
|
[Doc] Update doc about how to use the QuickLogic memory bank
|
2021-09-10 15:30:37 -07:00 |
|
tangxifan
|
801b91f776
|
Merge branch 'master' into tutorials
|
2021-08-31 17:17:40 -07:00 |
ANDREW HARRIS POND
|
1c09b8c3e0
|
fixed python instruction
|
2021-08-17 10:18:51 -06:00 |
bbleaptrot
|
814d290463
|
Merge branch 'master' into tutorials
|
2021-08-05 10:24:34 -06:00 |
|
bbleaptrot
|
c867c7e628
|
Update index to include FAQ page
|
2021-07-28 10:14:31 -06:00 |
|
bbleaptrot
|
2bb76e4a82
|
Update to include suggested changes
|
2021-07-28 10:13:25 -06:00 |
|
bbleaptrot
|
17d3fb5d5e
|
Add FAQ to source folder to go along in appendix
|
2021-07-28 10:10:17 -06:00 |
Andrew Pond
|
a8a8c25a21
|
Update compile.rst
|
2021-07-26 15:18:23 -06:00 |
|
Andrew Pond
|
1c0bec1c5a
|
Update compile.rst
|
2021-07-26 15:17:25 -06:00 |
|
Andrew Pond
|
3ce866f2eb
|
Update compile.rst
|
2021-07-26 15:12:59 -06:00 |
|
tangxifan
|
43afaca17c
|
[Doc] Add more details about the new syntax
|
2021-07-01 23:51:54 -06:00 |
|
tangxifan
|
0851075bc9
|
[Doc] Update documentation about the new feature in pin constraint file
|
2021-07-01 23:47:36 -06:00 |
|
tangxifan
|
ac9046b7d2
|
[Doc] Remove ``define_simulation.v`` since it is no longer needed.
|
2021-06-29 15:38:35 -06:00 |
|
tangxifan
|
30027b8c15
|
[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'
|
2021-06-25 15:27:15 -06:00 |
|
tangxifan
|
11d0283771
|
[Doc] Remove option '--support_icarus_simulator'. Add option '--embed_bitstream'
|
2021-06-25 15:11:12 -06:00 |
|
tangxifan
|
507f5ee54c
|
[Doc] Update documentation about time unit support in writing simulation file
|
2021-06-25 10:34:43 -06:00 |
|
tangxifan
|
8e2ba718d0
|
[Doc] update documentation on the new option '--testbench_type'
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2021-06-25 10:16:48 -06:00 |
|
tangxifan
|
779437cd37
|
[Doc] Update documentation to remove out-of-date options related to signal_init
|
2021-06-24 17:07:15 -06:00 |
|
bbleaptrot
|
de550ac550
|
Merge branch 'master' into tutorials
|
2021-06-16 14:00:31 -06:00 |
|
bbleaptrot
|
7787fe9795
|
update reference to match doc page
|
2021-06-16 12:46:43 -06:00 |
|
bbleaptrot
|
858bb2f21e
|
fix mistake in first line of page
|
2021-06-16 12:45:04 -06:00 |
|
bbleaptrot
|
624e9f3bb7
|
Update notation at top to match pages in doc
|
2021-06-16 12:44:01 -06:00 |
|
bbleaptrot
|
ece6e92f06
|
Add video at top of page
|
2021-06-16 12:29:17 -06:00 |
|
bbleaptrot
|
7a303463c3
|
Update shell_shortcuts.rst
Update grammar. <_openfpga_task_args> no longer works
|
2021-06-14 15:34:13 -06:00 |
|
bbleaptrot
|
5e8b5d641f
|
Update compile.rst
update grammar
|
2021-06-14 14:51:19 -06:00 |
|
bbleaptrot
|
1a2ced678e
|
Update tech_highlights.rst
Update grammar and add link to standard_cell_library tutorial
|
2021-06-14 14:34:12 -06:00 |
|
bbleaptrot
|
d0549f10b3
|
Make a :ref: for tutorial
|
2021-06-14 14:28:21 -06:00 |
|
tangxifan
|
9585e1d3b5
|
[Doc] Update documentation about 'default_net_type' option in testbench generators
|
2021-06-14 14:00:34 -06:00 |
|
bbleaptrot
|
dc13325639
|
Update motivation.rst
Fixing grammar and spacing
|
2021-06-14 13:44:20 -06:00 |
|
tangxifan
|
b719419931
|
[Doc] Update documentation on the FPGA-Verilog commands in openfpga shell; Deprecated the 'write_verilog_testbench' command
|
2021-06-09 16:59:02 -06:00 |
|
tangxifan
|
54a53bc988
|
[Doc] Update documentation on the minor changes on bitstream file for memory bank protocol
|
2021-06-07 17:58:00 -06:00 |
|
tangxifan
|
0fee741008
|
[Doc] Update documentation on the minor changes on fabric bitstream file format
|
2021-06-07 14:22:35 -06:00 |