tangxifan
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2e6b311d04
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[core] add more details to debug messages
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2024-08-02 18:33:43 -07:00 |
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tangxifan
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eeaa3373c6
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[core] code format
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2024-08-02 17:48:47 -07:00 |
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tangxifan
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82cf7bbb8c
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[core] Add verbose mode on find_node() for clock rr graph
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2024-08-02 17:47:41 -07:00 |
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tangxifan
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1ec5847d5a
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[core] typo
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2024-08-02 14:27:43 -07:00 |
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tangxifan
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f44c45bdd3
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[core] code format
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2024-08-02 14:23:35 -07:00 |
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tangxifan
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f7e30b9974
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[core] fixed a bug where pb pin fixup does not support perimeter cb
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2024-08-02 14:21:22 -07:00 |
chungshien
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b3c8c529d5
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Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-31 12:25:37 -07:00 |
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tangxifan
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d6db51f29e
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[core] code format
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2024-07-30 19:09:31 -07:00 |
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tangxifan
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ef6b6f8e40
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[core] remove warnings
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2024-07-30 18:50:49 -07:00 |
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tangxifan
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ae95357991
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[core] code format
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2024-07-30 15:40:41 -07:00 |
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tangxifan
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a2c3af60d7
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[core] fixed a bug where unique cb module is not considered as entry point
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2024-07-30 15:39:44 -07:00 |
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tangxifan
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853883cd36
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[core] code format
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2024-07-30 12:56:03 -07:00 |
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tangxifan
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234eee19ae
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[core] revert
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2024-07-30 12:29:32 -07:00 |
chungshien-chai
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0d9f1a3c6b
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Forward searching the config bit + some minor refactor
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2024-07-28 19:12:34 -07:00 |
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chungshien-chai
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2a3d69aded
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Update code based on feedback
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2024-07-28 02:37:15 -07:00 |
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chungshien-chai
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cbe9a46f95
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Format and update doc
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2024-07-28 00:02:20 -07:00 |
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chungshien-chai
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933155b08f
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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chungshien-chai
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e60777d23e
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Use Bitstream Setting XML
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2024-07-26 01:36:49 -07:00 |
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chungshien-chai
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2ef362d53d
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Init support overwriting bitstream
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2024-07-25 17:40:46 -07:00 |
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tangxifan
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1513ea749b
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[core] supporting clk spine on the same direction
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2024-07-16 22:12:51 -07:00 |
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tangxifan
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18d12109fb
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[core] fixed a critical bug where cb port name using index is not considered on clock network entry
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2024-07-16 17:42:21 -07:00 |
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tangxifan
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c1f46c448a
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[core] fixed a critical bug where clock network entry is on a CHANY
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2024-07-16 17:04:44 -07:00 |
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tangxifan
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cbd10e1222
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[core] fixed a bug where tile module's global port is not derived from dedicated clock network
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2024-07-16 16:58:21 -07:00 |
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tangxifan
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f607987386
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[core] patch the out-of-range in clock rr nodes
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2024-07-16 16:45:55 -07:00 |
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tangxifan
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c96f899c53
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[core] code format
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2024-07-10 15:07:26 -07:00 |
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tangxifan
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a4538fb25b
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[core] now supports to_pin in building clock network for internal driver
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2024-07-10 15:01:18 -07:00 |
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tangxifan
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215de8eb93
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[core] code format
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2024-07-10 14:17:22 -07:00 |
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tangxifan
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f5ba43e392
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[core] fixed a bug where rst internal net is used to wire global ports of fpga fabric in verilog testbench
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2024-07-10 14:16:24 -07:00 |
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tangxifan
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213914e4ac
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[core] code format
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2024-07-10 12:23:57 -07:00 |
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tangxifan
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48e159dd8d
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[core] fixed a bug where internal clock will be wired to fpga input pins in verilog testbenches
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2024-07-10 12:23:15 -07:00 |
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tangxifan
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c6dd33a965
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[core] fixed a bug when annotating global nets on OPIN
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2024-07-10 11:59:25 -07:00 |
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tangxifan
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96bdcc8b35
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[core] code format
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2024-07-09 22:54:55 -07:00 |
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tangxifan
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27e29f949c
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[core] fixed a bug where the pin idx of global net on rr graph is not well annotated
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2024-07-09 22:53:12 -07:00 |
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tangxifan
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092b8b038f
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[core] remove verbose out
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2024-07-08 22:23:37 -07:00 |
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tangxifan
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04504e4d5d
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[core] code format
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2024-07-08 22:22:59 -07:00 |
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tangxifan
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1cdb1c5995
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[core] fixed a bug on calculating subtile pins
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2024-07-08 22:22:08 -07:00 |
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tangxifan
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fe06c2f2b1
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[core] code format
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2024-07-08 16:18:58 -07:00 |
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tangxifan
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db459b0e87
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[core] add verbose outputs
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2024-07-08 16:18:32 -07:00 |
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tangxifan
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e8f9deeeaf
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[core] fixed a critical bug on computing pin index for subtile in clock taps
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2024-07-08 16:12:20 -07:00 |
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tangxifan
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6dde383a7f
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[core] debugging
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2024-07-08 16:00:18 -07:00 |
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tangxifan
|
8bca3d79be
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[core] fixed a bug where tap points of clock network cannot reach perimeter cb
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2024-07-08 15:17:24 -07:00 |
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tangxifan
|
7bd60f5f7d
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[core] support perimeter cb when identify pins of I/Os tiles
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2024-07-08 12:39:54 -07:00 |
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tangxifan
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5c9c4d93c5
|
[core] typo
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2024-07-08 10:46:47 -07:00 |
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tangxifan
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cdd477ad80
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[core] remove restrictions on cb clock nodes
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2024-07-08 10:14:39 -07:00 |
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tangxifan
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8449da0143
|
[core] typo
|
2024-07-07 23:36:13 -07:00 |
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tangxifan
|
7996de3fe6
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[core] now support perimeter cb in programmable clock network arch
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2024-07-07 14:57:05 -07:00 |
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tangxifan
|
703cbddc9e
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[core] code format
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2024-07-06 12:14:57 -07:00 |
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tangxifan
|
6024e35f89
|
[core] fixed a bug
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2024-07-05 18:50:14 -07:00 |
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tangxifan
|
1f7fbfef64
|
[core] fixed a bug on inter-tile connections in top module
|
2024-07-05 18:19:22 -07:00 |
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tangxifan
|
e95b264965
|
[core] debugging
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2024-07-05 18:08:48 -07:00 |