tangxifan
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092b8b038f
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[core] remove verbose out
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2024-07-08 22:23:37 -07:00 |
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tangxifan
|
04504e4d5d
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[core] code format
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2024-07-08 22:22:59 -07:00 |
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tangxifan
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1cdb1c5995
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[core] fixed a bug on calculating subtile pins
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2024-07-08 22:22:08 -07:00 |
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tangxifan
|
fe06c2f2b1
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[core] code format
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2024-07-08 16:18:58 -07:00 |
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tangxifan
|
db459b0e87
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[core] add verbose outputs
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2024-07-08 16:18:32 -07:00 |
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tangxifan
|
e8f9deeeaf
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[core] fixed a critical bug on computing pin index for subtile in clock taps
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2024-07-08 16:12:20 -07:00 |
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tangxifan
|
6dde383a7f
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[core] debugging
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2024-07-08 16:00:18 -07:00 |
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tangxifan
|
8bca3d79be
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[core] fixed a bug where tap points of clock network cannot reach perimeter cb
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2024-07-08 15:17:24 -07:00 |
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tangxifan
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7bd60f5f7d
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[core] support perimeter cb when identify pins of I/Os tiles
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2024-07-08 12:39:54 -07:00 |
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tangxifan
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5c9c4d93c5
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[core] typo
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2024-07-08 10:46:47 -07:00 |
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tangxifan
|
cdd477ad80
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[core] remove restrictions on cb clock nodes
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2024-07-08 10:14:39 -07:00 |
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tangxifan
|
8449da0143
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[core] typo
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2024-07-07 23:36:13 -07:00 |
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tangxifan
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7996de3fe6
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[core] now support perimeter cb in programmable clock network arch
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2024-07-07 14:57:05 -07:00 |
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tangxifan
|
703cbddc9e
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[core] code format
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2024-07-06 12:14:57 -07:00 |
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tangxifan
|
6024e35f89
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[core] fixed a bug
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2024-07-05 18:50:14 -07:00 |
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tangxifan
|
1f7fbfef64
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[core] fixed a bug on inter-tile connections in top module
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2024-07-05 18:19:22 -07:00 |
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tangxifan
|
e95b264965
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[core] debugging
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2024-07-05 18:08:48 -07:00 |
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tangxifan
|
cca9fb4756
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[core] fixed a bug on bottom left tile organization
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2024-07-05 17:55:19 -07:00 |
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tangxifan
|
46d916f0a0
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[core] fixed the bugs in fabric tile build-up
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2024-07-05 16:59:08 -07:00 |
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tangxifan
|
a41f437109
|
[core] now netlist look ok
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2024-07-05 12:36:47 -07:00 |
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tangxifan
|
283aa3a1c9
|
[core] debug
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2024-07-05 12:21:17 -07:00 |
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tangxifan
|
46e3b4b071
|
[core] debug
|
2024-07-05 11:50:41 -07:00 |
|
tangxifan
|
fdbc427f70
|
[core] debug
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2024-07-05 11:17:05 -07:00 |
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tangxifan
|
f6adca1545
|
[core] fixed a bug
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2024-07-05 11:02:01 -07:00 |
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tangxifan
|
1dc602a849
|
[core] syntax
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2024-07-05 10:38:26 -07:00 |
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tangxifan
|
266c2686d4
|
[core] adapt new gsb coordinate system
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2024-07-05 10:32:33 -07:00 |
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tangxifan
|
1f8c2436ef
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[core] now constant_undriven_inputs are force to enable when perimeter_cb is selected
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2024-07-04 20:46:38 -07:00 |
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tangxifan
|
72ee39f178
|
[core] add new command line option 'constant_undriven_inputs'
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2024-07-04 20:39:02 -07:00 |
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tangxifan
|
4e21bbb3f1
|
[core] now support constant undriven local wires in verilog writer
|
2024-07-04 20:32:56 -07:00 |
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tangxifan
|
1dd03d0fdd
|
[core] on a new feature to connect undriven pins to ground
|
2024-07-04 18:34:39 -07:00 |
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tangxifan
|
6d798897fd
|
[lib] update vtr
|
2024-07-04 14:46:57 -07:00 |
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tangxifan
|
f560fb8381
|
[core] more verbose
|
2024-07-04 14:27:17 -07:00 |
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tangxifan
|
a8850d4f0f
|
[core] now verbose mode is applicable to more build top module cb instances
|
2024-07-04 14:22:30 -07:00 |
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tangxifan
|
4b53e57c92
|
[core] fixed a bug
|
2024-07-04 13:33:04 -07:00 |
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tangxifan
|
d2a68ff9c5
|
[core] now corner tile are considered as config child
|
2024-07-04 13:25:57 -07:00 |
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tangxifan
|
b80ed8d15c
|
[core] fixed a bug
|
2024-07-04 12:58:16 -07:00 |
|
tangxifan
|
a3723b33b3
|
[core] fixed a minor bug
|
2024-07-04 12:52:29 -07:00 |
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tangxifan
|
a717882304
|
[core] now when perimeter_cb is on, I/O pins can access three sides of routing tracks
|
2024-07-04 12:44:48 -07:00 |
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tangxifan
|
724c14d1f7
|
[core] fixed a bug on build top module connections on perimeter gsb when cbs occur
|
2024-07-04 11:09:01 -07:00 |
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tangxifan
|
550ce0c390
|
[core] fixed the bug on build gsb when cbs are on perimeters
|
2024-07-04 10:58:44 -07:00 |
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tangxifan
|
bc94e08c77
|
[lib] update vtr and fixing some bugs in annotate gsb when perimeter_cb is enabled
|
2024-07-03 22:28:22 -07:00 |
|
tangxifan
|
a27325d987
|
[core] code format
|
2024-07-03 17:05:27 -07:00 |
|
tangxifan
|
f681c6a903
|
[core] update API call due to vtr upgrade
|
2024-07-03 17:04:06 -07:00 |
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tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
|
tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
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tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
|
2024-06-29 17:35:47 -07:00 |
|
tangxifan
|
4f787a5cfc
|
[core] add more debugging message
|
2024-06-29 10:54:08 -07:00 |
|
tangxifan
|
5fa674be24
|
[core] fixed the bug on matching global net from pcf
|
2024-06-29 10:51:45 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |