tangxifan
|
f9f9aab7d9
|
[test] typo
|
2024-07-30 12:50:14 -07:00 |
|
tangxifan
|
ad275fba44
|
[test] add a new test to validate clock network entry point on a y-direction cb
|
2024-07-30 12:48:35 -07:00 |
|
tangxifan
|
e614ca7380
|
[test] use new syntax
|
2024-07-10 15:03:27 -07:00 |
|
tangxifan
|
977283dd34
|
[core] typo
|
2024-07-10 14:12:49 -07:00 |
|
tangxifan
|
af996e563e
|
[test] add a new test to validate reset generated by internal driver through programmable clock network
|
2024-07-10 14:11:06 -07:00 |
|
tangxifan
|
b6ff69faac
|
[test] reworking the testcase to validate clock network with internal drivers
|
2024-07-10 11:36:22 -07:00 |
|
tangxifan
|
dbe8e63f53
|
[test] remove unused files
|
2024-07-10 10:15:47 -07:00 |
|
tangxifan
|
77304164f4
|
[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
|
2024-07-10 10:13:41 -07:00 |
|
tangxifan
|
191a3d1c5e
|
[test] update W
|
2024-07-10 10:01:31 -07:00 |
|
tangxifan
|
81fe722d98
|
[test] adjust W
|
2024-07-09 23:49:01 -07:00 |
|
tangxifan
|
43dbeafd44
|
[test] typo
|
2024-07-09 20:27:28 -07:00 |
|
tangxifan
|
9ce4b57363
|
[test] typo
|
2024-07-09 20:25:39 -07:00 |
|
tangxifan
|
e5d146a67a
|
[test] add new tests to validate rst on lut and clk on lut features
|
2024-07-09 20:24:23 -07:00 |
|
tangxifan
|
5efc9d0e00
|
[test] update golden outputs
|
2024-07-08 23:24:16 -07:00 |
|
tangxifan
|
5cb104a5f6
|
[test] fixed a bug
|
2024-07-08 22:04:40 -07:00 |
|
tangxifan
|
c30eafac9f
|
[test] fixed a bug on clk ntwk arch where some io clocks are not tapped
|
2024-07-08 15:26:16 -07:00 |
|
tangxifan
|
b50acacfba
|
[test] fixed some bug in pin loc; Outputs are not recommend on the fringe I/O tiles
|
2024-07-08 15:09:31 -07:00 |
|
tangxifan
|
6492d43a01
|
[test] add a new test to validate perimeter cb using global tile clock
|
2024-07-08 11:29:20 -07:00 |
|
tangxifan
|
5c9c4d93c5
|
[core] typo
|
2024-07-08 10:46:47 -07:00 |
|
tangxifan
|
ff56139a53
|
[test] debugging
|
2024-07-07 23:07:51 -07:00 |
|
tangxifan
|
1a5e2392fc
|
[test] add a new testcase to validate clock network when perimeter cb is on
|
2024-07-07 22:32:13 -07:00 |
|
tangxifan
|
db12532eb8
|
[test] typo
|
2024-07-07 21:41:39 -07:00 |
|
tangxifan
|
439de61fd0
|
[test] fixed a bug on ecb support
|
2024-07-07 14:00:11 -07:00 |
|
tangxifan
|
a46820b7c1
|
[core] add a new test for bottom-left tile grouping
|
2024-07-05 18:00:37 -07:00 |
|
tangxifan
|
a78fddc3cb
|
[test] add a new testcase to validate perimeter cb
|
2024-07-03 19:59:24 -07:00 |
|
tangxifan
|
7e461b09f8
|
[core] add missing file
|
2024-07-02 13:22:41 -07:00 |
|
tangxifan
|
29452a7442
|
[test] fixed a bug on out-of-date arch
|
2024-07-02 11:52:19 -07:00 |
|
tangxifan
|
e00312d29e
|
[test] typo
|
2024-07-01 20:34:37 -07:00 |
|
tangxifan
|
1bfcf7574c
|
[test] validate region and single syntax
|
2024-07-01 20:33:28 -07:00 |
|
tangxifan
|
28e3cb799e
|
[test] update 2-clock arch and pcf
|
2024-06-29 17:40:20 -07:00 |
|
tangxifan
|
12c9686c27
|
[test] fixed some bugs on arch
|
2024-06-29 17:38:34 -07:00 |
|
tangxifan
|
5dd0549aed
|
[core] typo
|
2024-06-29 17:17:54 -07:00 |
|
tangxifan
|
bc2f02866d
|
[test] update testcase for 2-clk on programmable clock network
|
2024-06-29 17:17:05 -07:00 |
|
tangxifan
|
286df30947
|
[test] update clock arch xml syntax
|
2024-06-29 11:02:17 -07:00 |
|
tangxifan
|
67554cb8d8
|
[test] now use correct pcf for clock network testcases
|
2024-06-29 10:04:03 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
|
2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
|
2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
f1a4304ee7
|
[test] add new testcases for validate clock tree disable functions
|
2024-06-28 13:43:53 -07:00 |
|
tangxifan
|
ad5795bece
|
[test] add extra options to route clock rr_graph command in examples
|
2024-06-28 13:39:41 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
2cbb04b90d
|
[test] add a new testcase to validate programmable clock network with internal drivers
|
2024-06-25 11:58:05 -07:00 |
|
tangxifan
|
9bb076d892
|
[test] fixed a bug on pin mapping of tetbenche
|
2024-06-21 20:29:21 -07:00 |
|
tangxifan
|
8d7dba2d57
|
[test] add a new testcase to programmable clock network on supporting reset signals
|
2024-06-21 18:13:37 -07:00 |
|
tangxifan
|
6c5988575c
|
[test] update clock network testcase
|
2024-06-21 16:59:21 -07:00 |
|
tangxifan
|
4d9aacdf8f
|
[test] add and deploy new benchmark
|
2024-06-02 14:27:02 -07:00 |
|
tangxifan
|
ad2d101554
|
[test] deploy new benchmarks
|
2024-06-02 14:23:08 -07:00 |
|
tangxifan
|
8f2974d7a1
|
[test] update golden copies
|
2024-05-29 10:31:19 -07:00 |
|
tangxifan
|
f25081eb31
|
[test] add a new test to validate ecb when tile modules are used
|
2024-05-20 21:10:49 -07:00 |
|
tangxifan
|
852b01aaff
|
[test] rework
|
2024-05-20 17:20:04 -07:00 |
|
tangxifan
|
a9a5fbee34
|
[test] add fully connected feedback connections to directlist
|
2024-05-20 17:02:20 -07:00 |