9d8f4c1664
[script] format python codes
2022-11-21 14:21:31 -08:00
12d114bbae
[test] hit the bug of tileable rr_graph skip it
2022-11-05 10:52:04 -07:00
dc24e41c6b
[test] relax minW for counter128, as VPR's router degrades in routability
2022-11-03 19:48:13 -07:00
513f7800aa
[test] update golden outputs for no_cout_in_gsb testcase
2022-11-03 17:51:51 -07:00
a88bc2d4de
[test] update golden outputs for device4x4
2022-11-03 17:51:08 -07:00
5f74367c2e
[test] update golden for device1x1 no time stamp netlists
2022-11-03 17:48:40 -07:00
958ef37a83
Merge pull request #864 from yunuseryilmaz18/master
...
Update dpram16k.v, dpram_2048x8.v, and dpram1k.v
2022-10-30 12:16:21 -07:00
1abd6bca42
Merge branch 'master' into master
2022-10-27 10:18:59 -07:00
67a77d863e
Update dpram.v
2022-10-27 08:29:56 +03:00
0fe3bd36b6
Update dpram16k.v
2022-10-27 08:28:58 +03:00
74568b13a2
Update dpram1k.v
2022-10-26 16:32:14 +03:00
64b5b5c31c
Update dpram_2048x8.v
2022-10-26 16:31:16 +03:00
f8b170ba75
Update dpram16k.v
2022-10-26 16:27:30 +03:00
82d8630ed4
Merge branch 'master' into patch-3
2022-10-24 13:32:42 +03:00
40f1f2fbc6
[test] update golden results for iwls
2022-10-21 20:28:10 -07:00
04286508c8
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
2022-10-21 20:26:56 -07:00
62a437a3a1
Merge branch 'master' into patch-3
2022-10-21 09:41:26 -07:00
db0e5dff93
Added new cell library for fracturable dsp36
...
Added new divisible 36x36 multiplier cell library for architectures which has fracturable dsp36:
- The 36x36 multiplier is form from sixteen 9x9 multipliers.
- It operates same modes with existing library. It can operate in 3 fracturable modes:
1. one 36-bit multiplier
2. two 18-bit multipliers
3. four 9-bit multipliers
- It provides ~%20 better area than existing cell library (mult_36x36.v)
Comparison made with Synopsys Design Compiler NXT:
mult_36x36.v Total cell area 20470 um2
frac_mult_36x36.v Total cell area 15103 um2
2022-10-21 17:30:20 +03:00
29d4b3cced
Update frac_mem_32k.v
...
1. Mixed use of non-blocking and blocking statements are unsynthesizable in Synopsys Design Compiler.
2. While defining a multidimensional array, the first array size is for the length and the second one is for the depth. The order for ram_a and ram_b arrays was wrong and it caused "out of bounds" error in DC.
2022-10-20 09:48:29 +03:00
00a485cbeb
[test] add missing file
2022-10-17 19:44:25 -07:00
609e096b1a
[test] added a new test to validate explicit port direction in pin table support
2022-10-17 15:25:19 -07:00
8b00bfdff9
[test] replace hardcoded paths in task config files with relative paths
2022-10-17 11:55:57 -07:00
aa78981e37
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
2022-10-17 11:18:21 -07:00
e9ee039e60
Merge branch 'master' into rst_on_lut_strong
2022-10-13 16:01:57 -07:00
33e2b16cb1
[arch] fixed a bug which caused verification failed
2022-10-13 15:33:43 -07:00
1c36ac28f1
[arch] code format
2022-10-13 12:17:32 -07:00
32f48f16c7
[arch] fixed a few bugs
2022-10-13 11:54:58 -07:00
b0be27b384
[test] add repack design constraints files
2022-10-13 11:22:48 -07:00
5cf315958d
[test] deploy new test to basic regression tests
2022-10-13 11:17:34 -07:00
7b7217d116
[arch]add new arch to test
2022-10-13 11:08:51 -07:00
7f67794787
[arch]add new arch to test
2022-10-13 10:54:40 -07:00
d7a253408d
Update k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 14:00:59 +03:00
6f55371d4b
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_GlobalTile8Clk_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-13 13:53:32 +03:00
f62d435b1e
Update frac_mem_32k.v
2022-10-12 09:35:35 +03:00
35869b480a
Merge branch 'master' into xmllint
2022-10-07 10:47:43 -07:00
85089cbc88
[arch] apply xml format for all the architecture files
2022-10-07 10:31:51 -07:00
508c01cef6
Update k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
...
Mode port assertions should be bind with "physical_mode_port_rotate_offset" instead of "physical_mode_pin_rotate_offset".
2022-10-07 09:38:07 +03:00
ab53f88c2b
[test] now use a fixed device layout for the single-mode LUT design testcase
2022-10-04 10:05:22 -07:00
13c819bb28
[ci] deply new test to ci
2022-10-01 11:04:08 -07:00
4eaecde0b9
[test] add golden netlists to ensure no cout in gsb
2022-10-01 11:03:13 -07:00
78f30cf072
[test] add a new test to track the golden netlists where cout is not in GSB
2022-09-30 15:38:27 -07:00
0d8d8446ee
[test] fixed a bug where OPIN for direct connection is included in GSB
2022-09-30 15:24:51 -07:00
088ff1a474
[script] fixed a bug
2022-09-29 16:27:03 -07:00
0565ca7aca
[script] add missing files
2022-09-29 16:14:38 -07:00
a3e7133d63
Merge branch 'master' into wire_lut_test
2022-09-29 16:02:18 -07:00
2ed4a60f36
[arch] reduce clb inputs to force net remapping during routing
2022-09-29 15:52:30 -07:00
ce0fbe1765
[test] fixed a few bugs
2022-09-29 15:32:31 -07:00
9bc9b61d35
[test] fixed a few bugs
2022-09-29 15:11:30 -07:00
f5e7ec4dd1
[test] add a new test case to validate wire lut case
2022-09-29 14:28:59 -07:00
df1ae7ba2a
[benchmark] add a new benchmark to enhance the tests for wire-lut features in repacker
2022-09-29 14:23:17 -07:00
tangxifan
Yunus Emre ERYILMAZ
mustafa.arslan