tangxifan
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4f1d815d7b
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Merge pull request #173 from lnis-uofu/dev
Support Multiple Clock Definition in Testbench and SDC Generators
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2021-01-15 16:13:46 -07:00 |
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tangxifan
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b8e4675a3a
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[Tool] Add missing file
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2021-01-15 14:48:19 -07:00 |
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tangxifan
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c4d3e7c50c
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[Doc] Update documentation for the new XML syntax in simulation settings
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2021-01-15 12:30:26 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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89f9d24d32
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[Flow] Update simulation settings for multiple clock to allow unique clock port name
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2021-01-15 10:35:43 -07:00 |
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tangxifan
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dbed04b53b
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[Flow] Reduce the number of clock cycles to simulation in example sim setting XML for a light test run in CI
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2021-01-14 15:42:21 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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923f3a3401
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[Flow] Add an example simulation settings for a 4-clock FPGA fabric
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2021-01-13 17:29:39 -07:00 |
Ashton Snelgrove
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effe86fb9e
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Remove pull request trigger
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2021-01-13 17:16:39 -07:00 |
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tangxifan
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ec587a6d46
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Merge pull request #172 from lnis-uofu/dev
Basic Support on Multi-Clock Fabric Netlist Generation and Testbench Generation
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2021-01-13 17:14:56 -07:00 |
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Ashton Snelgrove
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afa55f1942
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Merge remote-tracking branch 'origin/master' into github-action-optimizations
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2021-01-13 17:07:54 -07:00 |
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Ashton Snelgrove
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2b705ba17a
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Add building a regression test image on master.
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2021-01-13 17:05:55 -07:00 |
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tangxifan
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2b959290e9
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[Test] Deploy multi-clock test to CI
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2021-01-13 15:44:19 -07:00 |
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tangxifan
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9a906e787b
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[Benchmark] Add post-yosys .v file for counter 4-bit with dual clock
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2021-01-13 15:43:31 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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c5a2027f36
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[Flow] Use implicit port mapping to avoid renaming problem between yosys and VPR
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2021-01-13 15:41:48 -07:00 |
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tangxifan
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7af6d7f07d
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[Benchmark] change the pin sequence of counter4bit_2clock to be easy for testbench generation
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2021-01-13 15:38:44 -07:00 |
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tangxifan
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9cc9e45b4b
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[Tool] Apply a dirty fix to Verilog testbench generator so that multi-clock testbench can be generated
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2021-01-13 15:13:19 -07:00 |
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Ashton Snelgrove
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4efa5b98e8
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Add docker distribution image.
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2021-01-13 13:58:20 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
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ccf3e037ff
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[Benchmark] Change multi-clock counter from 8-bit to 4-bit
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2021-01-13 13:31:06 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
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2f1aceda67
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[Doc] Update documentation about architecture naming rules
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2021-01-12 18:01:24 -07:00 |
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tangxifan
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9fa49c401c
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[Arch] Add openfpga architecture which uses 4 global clocks
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2021-01-12 18:00:22 -07:00 |
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tangxifan
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16b4e89326
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[Doc] Update documentation for VPR architectures
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2021-01-12 17:57:40 -07:00 |
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tangxifan
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7ccdff4543
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[Arch] Add an architecture using 4 clocks
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2021-01-12 17:55:57 -07:00 |
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tangxifan
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3790f2c26a
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[Benchmark] Add 2-clock micro benchmark
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2021-01-12 17:48:52 -07:00 |
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tangxifan
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a0b9f2b40d
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Merge pull request #170 from lnis-uofu/dev
Extended Support on Defining Global Ports from Physical Tile Ports
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2021-01-11 10:02:31 -07:00 |
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tangxifan
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30aaab0c2e
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[Test] Deploy new test to CI
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2021-01-10 11:53:49 -07:00 |
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tangxifan
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65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
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tangxifan
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e58e1e86c2
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[Test] Update test case to use new shell script
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2021-01-10 11:09:10 -07:00 |
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tangxifan
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18d2a8ce19
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[Flow] Add new script for fixed device layout using global tile clock
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2021-01-10 11:08:02 -07:00 |
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tangxifan
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aaf582acc5
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[Arch] Bug fix
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2021-01-10 11:05:57 -07:00 |
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tangxifan
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1c68e43acf
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[Test] Add new test case for registerable I/O architecture
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2021-01-10 11:00:21 -07:00 |
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tangxifan
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f21d22f691
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[Doc] Update README for new architectures
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2021-01-10 10:54:59 -07:00 |
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tangxifan
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dfb3e32147
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[Arch] Add openfpga archiecture for registerable I/O
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2021-01-10 10:54:41 -07:00 |
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tangxifan
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853e7b1a40
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[Arch] Add vpr architecture where I/O can be either combinational or registered
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2021-01-10 10:54:09 -07:00 |
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tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
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tangxifan
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6521aa2e7a
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[Benchmark] Bug fix in pipelined and2 benchmark
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2021-01-10 10:27:59 -07:00 |
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tangxifan
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4412bbd084
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[Benchmark] Add a micro benchmark to test pipelined architecture
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2021-01-10 10:21:30 -07:00 |
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tangxifan
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0c808bec41
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[Doc] Add clarification for defining multi-bit global tile ports
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2021-01-09 20:00:16 -07:00 |
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tangxifan
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4124777948
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[Tool] Set (x,y) to be optional XML syntax in tile annotation
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2021-01-09 18:56:41 -07:00 |
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tangxifan
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2324edc522
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[Doc] Update documentation for upgraded tile annotation
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2021-01-09 18:55:16 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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0b74575606
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[Arch] Update arch using global reset tile port
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2021-01-09 18:04:55 -07:00 |
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tangxifan
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7b24da267a
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[Arch] Remove port size XML syntax
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2021-01-09 16:30:46 -07:00 |
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tangxifan
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9f12b25a24
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[Arch] Add port size to global port defined thru tile annotation
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2021-01-09 16:23:28 -07:00 |