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3093 Commits

Author SHA1 Message Date
tangxifan 780be05079
Merge pull request #154 from lnis-uofu/dev 
Add pull request template
 2020-12-10 16:39:59 -07:00
Ashton Snelgrove d77aa19ae1 Run tests in parallel 2020-12-10 15:49:02 -07:00
Ashton Snelgrove faec0ea782 Github action optimizations 2020-12-10 14:35:19 -07:00
Lalit Sharma 0ee3efb306 Adding a testcase to run yosys quicklogic flow 2020-12-10 02:41:43 -08:00
Lalit Sharma f805a62f96 Updating yosys branch to quicklogic-rebased 2020-12-09 23:36:13 -08:00
Lalit Sharma 3b302dd538 Updating yosys URL to pick from QuickLogic-Corp repo, this is done till this repo is merged to mainstream repo 2020-12-09 22:25:51 -08:00
Lalit Sharma 760b8bd7ad Adding tcl8.6-dev package as CI dependency 2020-12-08 21:14:48 -08:00
Lalit Sharma 07dfd35e12 Adding yosys-symbiflow-plugins as submodule and adding tcllib as dependency in CI 2020-12-08 20:35:57 -08:00
tangxifan c278bb0a5f [Git] Format fix on pull request template 2020-12-08 17:29:30 -07:00
tangxifan e20c8d578e [Git] Format pull request template and add more OpenFPGA-related topics 2020-12-08 17:27:48 -07:00
tangxifan 6383946ae6 [Git] Add pull request template 2020-12-08 17:16:50 -07:00
tangxifan 6b50bbf986
Merge pull request #134 from lnis-uofu/ganesh_dev 
Support Delay Customization in OpenFPGA Task Configuration File
 2020-12-08 15:32:48 -07:00
Lalit Sharma 8a2681f99f Re-setting option YOSYS_ENABLE_TCL to ON, as yosys compilation depends on tcl 2020-12-08 09:21:25 -08:00
Lalit Sharma 3a7bc77871 Correcting the syntax for CI run 2020-12-08 09:14:05 -08:00
Lalit Sharma d7ec481e9e Adding updates to checkout submodules 2020-12-08 08:52:35 -08:00
Lalit Sharma ed9535693c Updating CMakeList.txt to compile yosys 2020-12-08 01:29:36 -08:00
Lalit Sharma 460bf9d3bd Adding yosys sub-module instead of yosys folder 2020-12-07 23:54:18 -08:00
Lalit Sharma 9cee60ddbf deleting yosys local folder to replace it with corresponding yosys sub-module 2020-12-07 23:52:20 -08:00
Laboratory for Nano Integrated Systems (LNIS) c5d9bac126
Merge pull request #150 from lnis-uofu/dev 
Misc Updates
 2020-12-06 15:44:37 -07:00
tangxifan d11a3d9fef [Tool] Avoid outputting signal initialization codes because they are bulky 2020-12-06 14:29:16 -07:00
tangxifan cb2bd2e31c [Tool] Remove register ports for mini local encoders (1-bit data out) 2020-12-06 14:21:54 -07:00
Laboratory for Nano Integrated Systems (LNIS) 2eaff52c13
Merge pull request #149 from lnis-uofu/dev 
Netlist/Module size Reduction for Routing Multiplexers
 2020-12-05 13:44:20 -07:00
tangxifan 6bdfcb0147 [Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming 2020-12-05 12:44:09 -07:00
tangxifan 6f18688f0e [Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module 2020-12-05 10:53:01 -07:00
Laboratory for Nano Integrated Systems (LNIS) e1563c93d8
Merge pull request #148 from lnis-uofu/dev 
Organize Routing Multiplexer Verilog Netlist
 2020-12-05 09:34:49 -07:00
tangxifan 0da92ad888 [Tool] Split MUX Verilog netlist into two separated files: one contains only primitives while the other contains the top-level modules 2020-12-04 22:16:51 -07:00
Laboratory for Nano Integrated Systems (LNIS) 09fa83ddfc
Merge pull request #147 from lnis-uofu/dev 
Support I/O tiles in the center part of FPGA grid layout
 2020-12-04 19:30:31 -07:00
tangxifan b717903ca1 [CI] Deploy new test to CI 2020-12-04 18:51:30 -07:00
tangxifan 5be9e9b736 [Tool] Adapted tools to support I/O in center grid 2020-12-04 18:50:13 -07:00
tangxifan 6001da3a40 [Arch] Bug fix in tileable I/O arch example 2020-12-04 17:56:54 -07:00
tangxifan 73aaa261d8 [Tool] Relax the IO restriction in pb_pin post-routing packing fix-up 2020-12-04 17:55:25 -07:00
tangxifan 95c9e19901 [Tool] Tileable rr_graph now accept I/Os in center grid 2020-12-04 17:43:35 -07:00
tangxifan 1d0bdcfeca [Arch] Simplify the grid layout modeling 2020-12-04 17:38:44 -07:00
tangxifan 7206cafc0e [Tool] Minor bug fix 2020-12-04 17:18:02 -07:00
tangxifan 1c3f625e41 [Arch] Force empty tiles at corners for tileable I/O arch example 2020-12-04 17:11:06 -07:00
tangxifan 29fd13a42a [Tool] Relax restrictions on I/O location in tileable rr_graph builder 2020-12-04 17:07:01 -07:00
tangxifan 0cb8457e21 [Test] Add test case for tileable I/O 2020-12-04 16:02:47 -07:00
tangxifan 186eb0f0a4 [Arch] Add tileable I/O architecture example 2020-12-04 15:59:39 -07:00
Laboratory for Nano Integrated Systems (LNIS) f2e5261d80
Merge pull request #146 from lnis-uofu/dev 
Bug fix in LUT circuit model documentation
 2020-12-04 15:49:05 -07:00
tangxifan 406edeec89 [Doc] Typo fix 2020-12-04 15:07:02 -07:00
tangxifan 4fe190fa7e [Doc] Bug fix in LUT circuit model documentation 2020-12-04 14:44:27 -07:00
ganeshgore 289d9d2169 [Bugfix] Honors yosys_tmpl parameter in flow script 2020-12-03 12:24:24 -07:00
Laboratory for Nano Integrated Systems (LNIS) 3caf696422
Merge pull request #144 from lnis-uofu/dev 
Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches
 2020-12-03 09:57:19 -07:00
tangxifan 4aa6264b1c [Tool] Rework simulation time period to be sync with actual stimuli 2020-12-02 22:58:13 -07:00
tangxifan b661c39b04 [Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches 2020-12-02 19:36:36 -07:00
tangxifan d71f0537bc
Merge pull request #143 from lnis-uofu/dev 
Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port
 2020-12-02 18:41:25 -07:00
tangxifan 412fb5bb31 [Arch] Bug fix due to valid default value parser 2020-12-02 17:51:50 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan d195b9e32c [Tool] Bug fix in XML syntax to define default values for a global tile port 2020-12-02 17:03:48 -07:00
Laboratory for Nano Integrated Systems (LNIS) 621f989c9b
Merge pull request #141 from LNIS-Projects/dev 
Add a Test Case to CI which defines global reset port through tile port in VPR architecture
 2020-12-01 08:41:57 -07:00