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Merge pull request #148 from lnis-uofu/dev 

Organize Routing Multiplexer Verilog Netlist
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Laboratory for Nano Integrated Systems (LNIS) 2020-12-05 09:34:49 -07:00 committed by GitHub
parent 09fa83ddfc 0da92ad888
commit e1563c93d8
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 81 additions and 12 deletions
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1
openfpga/src/fpga_verilog/verilog_constants.h
View File

@ -32,6 +32,7 @@ constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";
constexpr char* ROUTING_VERILOG_FILE_NAME = "routing.v";
constexpr char* MUX_PRIMITIVES_VERILOG_FILE_NAME = "mux_primitives.v";
constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v";
constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v";
constexpr char* ARCH_ENCODER_VERILOG_FILE_NAME = "arch_encoder.v";

92
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -1218,19 +1218,19 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
}
}
/***********************************************
* Generate Verilog modules for all the unique
* Generate primitive Verilog modules for all the unique
* multiplexers in the FPGA device
**********************************************/
void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
std::string verilog_fname(submodule_dir + std::string(MUXES_VERILOG_FILE_NAME));
static
void print_verilog_submodule_mux_primitives(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
/* Output primitive cells for MUX modules */
std::string verilog_fname(submodule_dir + std::string(MUX_PRIMITIVES_VERILOG_FILE_NAME));
/* Create the file stream */
std::fstream fp;
@ -1239,10 +1239,10 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
check_file_stream(verilog_fname.c_str(), fp);
/* Print out debugging information for if the file is not opened/created properly */
VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...",
VTR_LOG("Writing Verilog netlist for Multiplexer primitives '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexers");
print_verilog_file_header(fp, "Multiplexer primitives");
/* Generate basis sub-circuit for unique branches shared by the multiplexers */
for (auto mux : mux_lib.muxes()) {
@ -1258,6 +1258,44 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
}
}
/* Close the file stream */
fp.close();
/* Add fname to the netlist name list */
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}
/***********************************************
* Generate top-level Verilog modules for all the unique
* multiplexers in the FPGA device
**********************************************/
static
void print_verilog_submodule_mux_top_modules(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
/* Output top-level MUX modules */
std::string verilog_fname(submodule_dir + std::string(MUXES_VERILOG_FILE_NAME));
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_stream(verilog_fname.c_str(), fp);
/* Print out debugging information for if the file is not opened/created properly */
VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexers");
/* Generate unique Verilog modules for the multiplexers */
for (auto mux : mux_lib.muxes()) {
const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
@ -1277,4 +1315,34 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
VTR_LOG("Done\n");
}
/***********************************************
* Generate Verilog modules for all the unique
* multiplexers in the FPGA device
* Output to two Verilog netlists:
* - A Verilog netlist contains all the primitive
* cells for build the routing multiplexers
* - A Verilog netlist contains all the top-level
* module for routing multiplexers
**********************************************/
void print_verilog_submodule_muxes(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const bool& use_explicit_port_map) {
print_verilog_submodule_mux_primitives(module_manager,
netlist_manager,
mux_lib,
circuit_lib,
submodule_dir,
use_explicit_port_map);
print_verilog_submodule_mux_top_modules(module_manager,
netlist_manager,
mux_lib,
circuit_lib,
submodule_dir,
use_explicit_port_map);
}
} /* end namespace openfpga */