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OpenFPGA
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5706 Commits

Author SHA1 Message Date
tangxifan 5a50fa84d1 keep updating fpga_flow.pl to use system call 2019-07-03 22:57:43 -06:00
tangxifan d64aeef5c4 add profiling to routing compact process 2019-07-03 16:57:34 -06:00
tangxifan 1a1da30ae9 fixed a critical bug in using tileable route chan W 2019-07-03 16:46:43 -06:00
tangxifan 6b894640c7 bug fixing in fpga_flow.pl 2019-07-03 14:59:05 -06:00
tangxifan b79d276ea9 add profiling to fpga_x2p_setup 2019-07-03 14:44:54 -06:00
tangxifan d5137eb424 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing 2019-07-03 14:31:18 -06:00
tangxifan 5195faab8b Merge branch 'dev' into tileable_routing 2019-07-03 14:30:39 -06:00
tangxifan 4f3cb0bdf3 added tileable routing chanW adaption to fixed W router 2019-07-03 14:29:50 -06:00
Ganesh Gore 443a73954f Removed all local files 
+ Removed local configurations and scripts from previous commit
 2019-07-03 14:26:06 -06:00
tangxifan c9743e84da Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-03 14:12:47 -06:00
tangxifan 45b00e0881 Merge branch 'dev' into tileable_routing 2019-07-03 14:11:45 -06:00
tangxifan a539c6a2a7 bug fixing in fpga_flow.pl 2019-07-03 14:11:14 -06:00
Ganesh Gore 57ad71438b Merging ganesh_dev to dev 
- Added spice_tool option in fpga_flow
- Some local customization
 2019-07-03 13:39:52 -06:00
AurelienUoU e13c703709 Upload recent commit 
Merge remote-tracking branch 'origin/dev' into heterogeneous
 2019-07-03 13:09:34 -06:00
AurelienUoU 43e9d8afd1 Add compact routing hierarchy option in fpga_flow 2019-07-03 13:08:49 -06:00
Ganesh Gore 3c36a51011 Added 'rewrite_path_in_file' back to repository 2019-07-03 12:49:25 -06:00
Ganesh Gore 53486b8a89 Added 'spice_simulator_path' in fpga_flow 
added vpr_fpga_spice_simulator_path in fpga-flow script
 2019-07-03 12:30:56 -06:00
tangxifan 570f9495e6 Merge branch 'tileable_routing' into dev 2019-07-03 12:13:48 -06:00
tangxifan 0c3e8bb70a add a new option to the router to enable conversion of route_chan_width to be tileable 2019-07-03 12:11:48 -06:00
AurelienUoU e0793c891a Update demo 2019-07-03 12:04:55 -06:00
tangxifan ea7e119313 Merge branch 'tileable_routing' into dev 2019-07-03 10:37:27 -06:00
tangxifan 02398818a9 update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area 2019-07-03 10:33:02 -06:00
tangxifan 547c479d84 Merge branch 'tileable_routing' into dev 2019-07-02 16:26:51 -06:00
tangxifan 4392c6bc3a bug fixing in fpga_flow scripts and add more print-out message for VPR 2019-07-02 15:34:59 -06:00
Baudouin Chauviere b08513d902 Big chunk added on the routing part of the explicit mapping 2019-07-02 14:12:42 -06:00
tangxifan 3e2a4917f5 Merge branch 'tileable_routing' into dev 2019-07-02 10:37:25 -06:00
AurelienUoU 60f7ab0465 Start heterogeneous dev 2019-07-02 10:16:10 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
tangxifan 95674c4687 added Switch Block SubType and SubFs for tileable rr_graph generation 2019-07-02 10:00:02 -06:00
Laboratory for Nano Integrated Systems (LNIS) e2b7636229
Merge pull request #6 from LNIS-Projects/multimode_clb 
Multimode clb
 2019-07-02 09:48:24 -06:00
tangxifan 44301bfd77 updated SPICE generator to avoid issues on clb2clb_direct 2019-07-02 09:01:52 -06:00
tangxifan 5b25bbb120 bug fixed for direct connection in CBs and direct connection in top netlist 2019-07-01 17:25:00 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
Baudouin Chauviere 0e04b88c8f Include new files in the parameter spreading 2019-07-01 11:27:48 -06:00
Ganesh Gore 54f6ca2687 Added lattice benchmark settings 2019-07-01 11:07:23 -06:00
tangxifan c54f3905d5 fixed broken fpga flow 2019-06-28 13:07:04 -06:00
tangxifan 1332ba62e8 update tileable rr_graph generator to improve routability and also enable assoicated testing 2019-06-27 17:52:25 -06:00
tangxifan 15c536e9b4 minor fixing in printing the rr_node stats 2019-06-27 16:34:21 -06:00
Baudouin Chauviere 04eb6d3488 Correction pre-merge 2019-06-27 14:33:06 -06:00
Ganesh Gore 11e6350214 Merge remote-tracking branch 'origin/multimode_clb' into ganesh_dev 2019-06-27 14:22:40 -06:00
Baudouin Chauviere 7c742f1cbb Stable, is_explicit propagated through the code. Not implemented though except for muxes 2019-06-27 10:29:57 -06:00
tangxifan 8edd85c9fc keep fixing bugs in verilog SDC generator for tileable CBs 2019-06-26 22:58:52 -06:00
tangxifan 711e369fe7 fixing bugs in the SDC generator and report_timing 2019-06-26 18:09:09 -06:00
tangxifan 0fe54d87d5 fixed a bug in SDC generator for constraining SBs in tileable arch 2019-06-26 17:06:14 -06:00
Baudouin Chauviere 0ce9846e47 Stable, unfinished 2019-06-26 16:54:41 -06:00
tangxifan 7d85eb544d start fixing bugs for SDC generator when using tileable arch 2019-06-26 16:48:17 -06:00
tangxifan f5920c7422 fix bugs in ptc_num using for SB 2019-06-26 16:21:02 -06:00
tangxifan 3d8200e217 critical bug fixed in bitstream generator for compact routing hierarchy 2019-06-26 15:51:11 -06:00