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Merge branch 'tileable_routing' into dev

This commit is contained in:
tangxifan 2019-07-03 12:13:48 -06:00
parent ea7e119313 0c3e8bb70a
commit 570f9495e6
12 changed files with 81 additions and 0 deletions
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5
fpga_flow/scripts/fpga_flow.pl
View File

@ -155,6 +155,7 @@ sub print_usage()
print " \t-vpr_place_clb_pin_remap: turn on place_clb_pin_remap in VPR.\n";
print " \t-vpr_max_router_iteration <int> : specify the max router iteration in VPR.\n";
print " \t-vpr_route_breadthfirst : use the breadth-first routing algorithm of VPR.\n";
print " \t-vpr_use_tileable_route_chan_width: turn on the conversion to tileable_route_chan_width in VPR.\n";
print " \t-min_route_chan_width <float> : turn on routing with <float>* min_route_chan_width.\n";
print " \t-fix_route_chan_width : turn on routing with a fixed route_chan_width, defined in benchmark configuration file.\n";
print " [ VPR - FPGA-X2P Extension ] \n";
@ -322,6 +323,7 @@ sub opts_read()
&read_opt_into_hash("ace_d","on","off");
&read_opt_into_hash("vpr_timing_pack_off","off","off");
&read_opt_into_hash("vpr_route_breadthfirst","off","off");
&read_opt_into_hash("vpr_use_tileable_route_chan_width","off","off");
&read_opt_into_hash("min_route_chan_width","on","off");
&read_opt_into_hash("fix_route_chan_width","off","off");
&read_opt_into_hash("vpr_max_router_iteration","on","off");
@ -1313,6 +1315,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $)
if (($fix_chan_width > 0)||($fix_chan_width == 0)) {
$chan_width_opt = "-route_chan_width $fix_chan_width";
}
if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) {
$chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width";
}
# FPGA SPICE options
my ($vpr_spice_opts) = ("");

2
vpr7_x2p/vpr/SRC/base/OptionTokens.c
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@ -57,6 +57,8 @@ struct s_TokenPair OptionBaseTokenList[] = {
{ "power_output_file", OT_POWER_OUT_FILE }, /* Output file for power results */
{ "power", OT_POWER }, /* Run power estimation? */
{ "tech_properties", OT_CMOS_TECH_BEHAVIOR_FILE }, /* Technology properties */
/* Xifan Tang: Tileable routing support !!! */
{ "use_tileable_route_chan_width", OT_USE_TILEABLE_ROUTE_CHAN_WIDTH}, /* Enable adaption to tileable route chan_width */
/* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */
{ "fpga_x2p_rename_illegal_port", OT_FPGA_X2P_RENAME_ILLEGAL_PORT }, /* Xifan TANG: rename illegal port names */
{ "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */

2
vpr7_x2p/vpr/SRC/base/OptionTokens.h
View File

@ -74,6 +74,8 @@ enum e_OptionBaseToken {
OT_ACTIVITY_FILE,
OT_POWER_OUT_FILE,
OT_CMOS_TECH_BEHAVIOR_FILE,
/* Xifan Tang: Tileable routing support !!! */
OT_USE_TILEABLE_ROUTE_CHAN_WIDTH,
/* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */
OT_FPGA_X2P_RENAME_ILLEGAL_PORT,
OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */

4
vpr7_x2p/vpr/SRC/base/ReadOptions.c
View File

@ -474,6 +474,10 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) {
case OT_CMOS_TECH_BEHAVIOR_FILE:
return ReadString(Args, &Options->CmosTechFile);
/* Xifan Tang: Tileable routing support !!! */
case OT_USE_TILEABLE_ROUTE_CHAN_WIDTH:
return Args;
/* Xifan Tang: FPGA X2P Options*/
case OT_FPGA_X2P_RENAME_ILLEGAL_PORT:
return Args;

7
vpr7_x2p/vpr/SRC/base/SetupVPR.c
View File

@ -626,6 +626,13 @@ static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled,
if (Options.Count[OT_SHOW_PASS_TRANS]) {
is_show_pass_trans = TRUE;
}
/* END */
/* Xifan Tang: Tileable routing support !!! */
RouterOpts->use_tileable_route_chan_width = FALSE;
if (Options.Count[OT_USE_TILEABLE_ROUTE_CHAN_WIDTH]) {
RouterOpts->use_tileable_route_chan_width = TRUE;
}
/* END */
/* Depends on RouterOpts->router_algorithm */

2
vpr7_x2p/vpr/SRC/base/ShowSetup.c
View File

@ -207,6 +207,7 @@ static void ShowRouterOpts(INP struct s_router_opts RouterOpts) {
} else {
vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width);
}
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: %s\n", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n");
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac);
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor);
@ -260,6 +261,7 @@ static void ShowRouterOpts(INP struct s_router_opts RouterOpts) {
} else {
vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width);
}
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: ", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n");
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac);
vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor);

31
vpr7_x2p/vpr/SRC/base/place_and_route.c
View File

@ -27,6 +27,8 @@
/* CLB PIN REMAP */
#include "place_clb_pin_remap.h"
#include "tileable_chan_details_builder.h"
/******************* Subroutines local to this module ************************/
static int binary_search_place_and_route(struct s_placer_opts placer_opts,
@ -326,14 +328,31 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
udsd_multiplier = 2;
/* UDSD by AY End */
if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) {
current = router_opts.fixed_channel_width + 5 * udsd_multiplier;
low = router_opts.fixed_channel_width - 1 * udsd_multiplier;
} else {
current = max_pins_per_clb + max_pins_per_clb % 2; /* Binary search part */
/* End */
low = -1;
}
/* Xifan Tang: W estimation for tileable routing architecture */
/* Build the segment inf vector */
std::vector<t_segment_inf> segment_vec;
for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) {
segment_vec.push_back(segment_inf[iseg]);
}
if (TRUE == router_opts.use_tileable_route_chan_width) {
int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec);
vpr_printf(TIO_MESSAGE_INFO,
"Adapt routing channel width (%d) to be tileable: %d\n",
current, adapted_W);
current = adapted_W;
}
/* Constraints must be checked to not break rr_graph generator */
if (det_routing_arch.directionality == UNI_DIRECTIONAL) {
if (current % 2 != 0) {
@ -442,6 +461,7 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
if (low != -1) {
current = (high + low) / 2;
} else {
current = high / 2; /* haven't found lower bound yet */
}
@ -457,6 +477,7 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
final = high;
current = (high + low) / 2;
} else {
if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) {
/* FOR Wneed = f(Fs) search */
@ -468,10 +489,20 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts,
}
} else {
current = low * 2; /* Haven't found upper bound yet */
}
}
}
current = current + current % udsd_multiplier;
/* Xifan Tang: W estimation for tileable routing architecture */
if (TRUE == router_opts.use_tileable_route_chan_width) {
int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec);
vpr_printf(TIO_MESSAGE_INFO,
"Adapt routing channel width (%d) to be tileable: %d\n",
current, adapted_W);
current = adapted_W;
}
}
/* The binary search above occassionally does not find the minimum *

3
vpr7_x2p/vpr/SRC/base/vpr_api.c
View File

@ -146,6 +146,9 @@ void vpr_print_usage(void) {
"\t[--acc_fac <float>] [--first_iter_pres_fac <float>]\n");
vpr_printf(TIO_MESSAGE_INFO,
"\t[--bend_cost <float>] [--route_type global | detailed]\n");
/* Xifan Tang: Tileable routing support !!! */
vpr_printf(TIO_MESSAGE_INFO,
"\t[--use_tileable_route_chan_width ]\n");
vpr_printf(TIO_MESSAGE_INFO,
"\t[--verify_binary_search] [--route_chan_width <int>]\n");
vpr_printf(TIO_MESSAGE_INFO,

2
vpr7_x2p/vpr/SRC/base/vpr_types.h
View File

@ -759,6 +759,8 @@ struct s_router_opts {
boolean verify_binary_search;
boolean full_stats;
boolean doRouting;
/* Xifan Tang: option to enable adaption to tileable route channel width */
boolean use_tileable_route_chan_width;
};
/* All the parameters controlling the router's operation are in this *

19
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp
View File

@ -118,6 +118,25 @@ std::vector<size_t> get_num_tracks_per_seg_type(const size_t chan_width,
return result;
}
/************************************************************************
* Adapt the number of channel width to a tileable routing architecture
***********************************************************************/
int adapt_to_tileable_route_chan_width(int chan_width,
std::vector<t_segment_inf> segment_infs) {
int tileable_chan_width = 0;
/* Estimate the number of segments per type by the given ChanW*/
std::vector<size_t> num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width,
segment_infs,
true); /* Force to use the full segment group */
/* Sum-up the number of tracks */
for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) {
tileable_chan_width += num_tracks_per_seg_type[iseg];
}
return tileable_chan_width;
}
/************************************************************************
* Build details of routing tracks in a channel
* The function will

2
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h
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@ -4,6 +4,8 @@
#include "vpr_types.h"
#include "chan_node_details.h"
int adapt_to_tileable_route_chan_width(int chan_width, std::vector<t_segment_inf> segment_inf);
ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const size_t max_seg_length,
const enum e_side device_side,
const std::vector<t_segment_inf> segment_inf);

2
vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h
View File

@ -5,6 +5,8 @@
#include "vpr_types.h"
int adapt_to_tileable_route_chan_width(int chanW, t_segment_inf* segment_inf);
void build_tileable_unidir_rr_graph(INP const int L_num_types,
INP t_type_ptr types, INP const int L_nx, INP const int L_ny,
INP struct s_grid_tile **L_grid, INP const int chan_width,