Update demo
This commit is contained in:
AurelienUoU
parent
60f7ab0465
commit
e0793c891a
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@ -5,11 +5,11 @@
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my_pwd=$PWD
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fpga_flow_scripts=${my_pwd}/fpga_flow/scripts
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vpr_path=${my_pwd}/vpr7_x2p/vpr
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benchmark="pipelined_32b_adder"
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benchmark="pipelined_8b_adder"
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include_netlists="_include_netlists.v"
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compiled_file="compiled_$benchmark"
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tb_formal_postfix="_top_formal_verification_random_tb"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirname="${vpr_path}${benchmark}_Verilog"
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log_file="${benchmark}_sim.log"
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new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh"
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template_sh="${PWD}/ERI_demo/eri_demo.sh"
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@ -29,7 +29,7 @@ cd $my_pwd
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# Start the script -> run the fpga generation -> run the simulation -> check the log file
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source $new_reg_sh # Leave us in vpr folder
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iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix
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vvp $compiled_file -j 16 >> $log_file
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vvp $compiled_file -j 64 >> $log_file
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result=`grep "Succeed" $log_file`
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if ["$result" = ""]; then
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@ -3,7 +3,7 @@
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# Set variables
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# For FPGA-Verilog ONLY
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benchmark="pipelined_32b_adder"
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benchmark="pipelined_8b_adder"
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OpenFPGA_path="OPENFPGAPATHKEYWORD"
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verilog_output_dirname="${benchmark}_Verilog"
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verilog_output_dirpath="$vpr_path"
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@ -21,13 +21,17 @@ new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v"
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ff_keyword="GENERATED_DIR_KEYWORD"
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ff_include_path="$verilog_output_dirpath/$verilog_output_dirname"
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arch_ff_keyword="FFPATHKEYWORD"
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tb_formal_ext="_formal_random_top_tb.v"
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formal_postfix="_top_formal_verification"
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clk_unmapped="clk\[0:0\]"
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clk_mapped="clk_fm"
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# Remove previous designs
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#rm -rf $verilog_output_dirpath/$verilog_output_dirname
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rm -rf $verilog_output_dirpath/$verilog_output_dirname
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mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
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cd $fpga_flow_scripts
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#cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
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perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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@ -35,8 +39,14 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
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cd $vpr_path
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# Run VPR
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./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy
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./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp
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cd $fpga_flow_scripts
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perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path
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rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
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perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext}
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cd -
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sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v
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@ -1,61 +0,0 @@
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clk 0.5 0.2
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wen 0.5 0.2
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wen_st0 0.5 0.2
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wen_st1 0.5 0.2
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ren 0.5 0.2
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raddr[0] 0.5 0.2
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raddr[1] 0.5 0.2
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raddr[2] 0.5 0.2
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raddr[3] 0.5 0.2
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raddr[4] 0.5 0.2
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raddr[5] 0.5 0.2
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raddr[6] 0.5 0.2
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raddr[7] 0.5 0.2
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raddr[8] 0.5 0.2
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raddr[9] 0.5 0.2
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raddr[10] 0.5 0.2
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waddr[0] 0.5 0.2
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waddr[1] 0.5 0.2
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waddr[2] 0.5 0.2
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waddr[3] 0.5 0.2
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waddr[4] 0.5 0.2
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waddr[5] 0.5 0.2
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waddr[6] 0.5 0.2
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waddr[7] 0.5 0.2
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waddr[8] 0.5 0.2
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waddr[9] 0.5 0.2
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waddr[10] 0.5 0.2
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waddr_st0[0] 0.5 0.2
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waddr_st0[1] 0.5 0.2
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waddr_st0[2] 0.5 0.2
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waddr_st0[3] 0.5 0.2
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waddr_st0[4] 0.5 0.2
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waddr_st0[5] 0.5 0.2
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waddr_st0[6] 0.5 0.2
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waddr_st0[7] 0.5 0.2
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waddr_st0[8] 0.5 0.2
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waddr_st0[9] 0.5 0.2
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waddr_st0[10] 0.5 0.2
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waddr_st1[0] 0.5 0.2
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waddr_st1[1] 0.5 0.2
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waddr_st1[2] 0.5 0.2
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waddr_st1[3] 0.5 0.2
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waddr_st1[4] 0.5 0.2
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waddr_st1[5] 0.5 0.2
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waddr_st1[6] 0.5 0.2
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waddr_st1[7] 0.5 0.2
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waddr_st1[8] 0.5 0.2
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waddr_st1[9] 0.5 0.2
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waddr_st1[10] 0.5 0.2
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a[0] 0.5 0.2
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a_st0[0] 0.5 0.2
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a_st1[0] 0.5 0.2
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b[0] 0.5 0.2
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b_st0[0] 0.5 0.2
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b_st1[0] 0.5 0.2
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q[0] 0.5 0.2
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q[1] 0.5 0.2
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AplusB[0] 0.5 0.2
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AplusB[1] 0.5 0.2
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cint01 0.5 0.2
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zero00 0 0
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@ -1,331 +0,0 @@
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clk 0.5 0.2
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wen 0.5 0.2
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wen_st0 0.5 0.2
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wen_st1 0.5 0.2
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ren 0.5 0.2
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raddr[0] 0.5 0.2
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raddr[1] 0.5 0.2
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raddr[2] 0.5 0.2
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raddr[3] 0.5 0.2
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raddr[4] 0.5 0.2
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raddr[5] 0.5 0.2
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raddr[6] 0.5 0.2
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raddr[7] 0.5 0.2
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raddr[8] 0.5 0.2
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raddr[9] 0.5 0.2
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raddr[10] 0.5 0.2
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waddr[0] 0.5 0.2
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waddr[1] 0.5 0.2
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waddr[2] 0.5 0.2
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waddr[3] 0.5 0.2
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waddr[4] 0.5 0.2
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waddr[5] 0.5 0.2
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waddr[6] 0.5 0.2
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waddr[7] 0.5 0.2
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waddr[8] 0.5 0.2
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waddr[9] 0.5 0.2
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waddr[10] 0.5 0.2
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waddr_st0[0] 0.5 0.2
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waddr_st0[1] 0.5 0.2
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waddr_st0[2] 0.5 0.2
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waddr_st0[3] 0.5 0.2
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waddr_st0[4] 0.5 0.2
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waddr_st0[5] 0.5 0.2
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waddr_st0[6] 0.5 0.2
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waddr_st0[7] 0.5 0.2
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waddr_st0[8] 0.5 0.2
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waddr_st0[9] 0.5 0.2
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waddr_st0[10] 0.5 0.2
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waddr_st1[0] 0.5 0.2
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waddr_st1[1] 0.5 0.2
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waddr_st1[2] 0.5 0.2
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waddr_st1[3] 0.5 0.2
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waddr_st1[4] 0.5 0.2
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waddr_st1[5] 0.5 0.2
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waddr_st1[6] 0.5 0.2
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waddr_st1[7] 0.5 0.2
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waddr_st1[8] 0.5 0.2
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waddr_st1[9] 0.5 0.2
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waddr_st1[10] 0.5 0.2
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a[0] 0.5 0.2
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a[1] 0.5 0.2
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a[2] 0.5 0.2
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a[3] 0.5 0.2
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a[4] 0.5 0.2
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a[5] 0.5 0.2
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a[6] 0.5 0.2
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a[7] 0.5 0.2
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a[8] 0.5 0.2
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a[9] 0.5 0.2
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a[10] 0.5 0.2
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a[11] 0.5 0.2
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a[12] 0.5 0.2
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a[13] 0.5 0.2
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a[14] 0.5 0.2
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a[15] 0.5 0.2
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a[16] 0.5 0.2
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a[17] 0.5 0.2
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a[18] 0.5 0.2
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a[19] 0.5 0.2
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a[20] 0.5 0.2
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a[21] 0.5 0.2
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a[22] 0.5 0.2
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a[23] 0.5 0.2
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a[24] 0.5 0.2
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a[25] 0.5 0.2
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a[26] 0.5 0.2
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a[27] 0.5 0.2
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a[28] 0.5 0.2
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a[29] 0.5 0.2
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a[30] 0.5 0.2
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a_st0[0] 0.5 0.2
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a_st0[1] 0.5 0.2
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a_st0[2] 0.5 0.2
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a_st0[3] 0.5 0.2
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a_st0[4] 0.5 0.2
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a_st0[5] 0.5 0.2
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a_st0[6] 0.5 0.2
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a_st0[7] 0.5 0.2
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a_st0[8] 0.5 0.2
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a_st0[9] 0.5 0.2
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a_st0[10] 0.5 0.2
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a_st0[11] 0.5 0.2
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a_st0[12] 0.5 0.2
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a_st0[13] 0.5 0.2
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a_st0[14] 0.5 0.2
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a_st0[15] 0.5 0.2
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a_st0[16] 0.5 0.2
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a_st0[17] 0.5 0.2
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a_st0[18] 0.5 0.2
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a_st0[19] 0.5 0.2
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a_st0[20] 0.5 0.2
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a_st0[21] 0.5 0.2
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a_st0[22] 0.5 0.2
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a_st0[23] 0.5 0.2
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a_st0[24] 0.5 0.2
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a_st0[25] 0.5 0.2
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a_st0[26] 0.5 0.2
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a_st0[27] 0.5 0.2
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a_st0[28] 0.5 0.2
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a_st0[29] 0.5 0.2
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a_st0[30] 0.5 0.2
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a_st1[0] 0.5 0.2
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a_st1[1] 0.5 0.2
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a_st1[2] 0.5 0.2
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a_st1[3] 0.5 0.2
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a_st1[4] 0.5 0.2
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a_st1[5] 0.5 0.2
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a_st1[6] 0.5 0.2
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a_st1[7] 0.5 0.2
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a_st1[8] 0.5 0.2
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a_st1[9] 0.5 0.2
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a_st1[10] 0.5 0.2
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a_st1[11] 0.5 0.2
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a_st1[12] 0.5 0.2
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a_st1[13] 0.5 0.2
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a_st1[14] 0.5 0.2
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a_st1[15] 0.5 0.2
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a_st1[16] 0.5 0.2
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a_st1[17] 0.5 0.2
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a_st1[18] 0.5 0.2
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a_st1[19] 0.5 0.2
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a_st1[20] 0.5 0.2
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a_st1[21] 0.5 0.2
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a_st1[22] 0.5 0.2
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a_st1[23] 0.5 0.2
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a_st1[24] 0.5 0.2
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a_st1[25] 0.5 0.2
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a_st1[26] 0.5 0.2
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a_st1[27] 0.5 0.2
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a_st1[28] 0.5 0.2
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a_st1[29] 0.5 0.2
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a_st1[30] 0.5 0.2
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b[0] 0.5 0.2
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b[1] 0.5 0.2
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b[2] 0.5 0.2
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b[3] 0.5 0.2
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b[4] 0.5 0.2
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b[5] 0.5 0.2
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b[6] 0.5 0.2
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b[7] 0.5 0.2
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b[8] 0.5 0.2
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b[9] 0.5 0.2
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b[10] 0.5 0.2
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b[11] 0.5 0.2
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b[12] 0.5 0.2
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b[13] 0.5 0.2
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b[14] 0.5 0.2
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b[15] 0.5 0.2
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b[16] 0.5 0.2
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b[17] 0.5 0.2
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b[18] 0.5 0.2
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b[19] 0.5 0.2
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b[20] 0.5 0.2
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b[21] 0.5 0.2
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b[22] 0.5 0.2
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b[23] 0.5 0.2
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b[24] 0.5 0.2
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b[25] 0.5 0.2
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b[26] 0.5 0.2
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b[27] 0.5 0.2
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b[28] 0.5 0.2
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b[29] 0.5 0.2
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b[30] 0.5 0.2
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b_st0[0] 0.5 0.2
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b_st0[1] 0.5 0.2
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b_st0[2] 0.5 0.2
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b_st0[3] 0.5 0.2
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b_st0[4] 0.5 0.2
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b_st0[5] 0.5 0.2
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b_st0[6] 0.5 0.2
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b_st0[7] 0.5 0.2
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b_st0[8] 0.5 0.2
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b_st0[9] 0.5 0.2
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b_st0[10] 0.5 0.2
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b_st0[11] 0.5 0.2
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b_st0[12] 0.5 0.2
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b_st0[13] 0.5 0.2
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b_st0[14] 0.5 0.2
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b_st0[15] 0.5 0.2
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b_st0[16] 0.5 0.2
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b_st0[17] 0.5 0.2
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b_st0[18] 0.5 0.2
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b_st0[19] 0.5 0.2
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b_st0[20] 0.5 0.2
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b_st0[21] 0.5 0.2
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b_st0[22] 0.5 0.2
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b_st0[23] 0.5 0.2
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b_st0[24] 0.5 0.2
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b_st0[25] 0.5 0.2
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b_st0[26] 0.5 0.2
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b_st0[27] 0.5 0.2
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b_st0[28] 0.5 0.2
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b_st0[29] 0.5 0.2
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b_st0[30] 0.5 0.2
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b_st1[0] 0.5 0.2
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b_st1[1] 0.5 0.2
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b_st1[2] 0.5 0.2
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b_st1[3] 0.5 0.2
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b_st1[4] 0.5 0.2
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b_st1[5] 0.5 0.2
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b_st1[6] 0.5 0.2
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b_st1[7] 0.5 0.2
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b_st1[8] 0.5 0.2
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b_st1[9] 0.5 0.2
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b_st1[10] 0.5 0.2
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b_st1[11] 0.5 0.2
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b_st1[12] 0.5 0.2
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b_st1[13] 0.5 0.2
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b_st1[14] 0.5 0.2
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b_st1[15] 0.5 0.2
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b_st1[16] 0.5 0.2
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b_st1[17] 0.5 0.2
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b_st1[18] 0.5 0.2
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b_st1[19] 0.5 0.2
|
||||
b_st1[20] 0.5 0.2
|
||||
b_st1[21] 0.5 0.2
|
||||
b_st1[22] 0.5 0.2
|
||||
b_st1[23] 0.5 0.2
|
||||
b_st1[24] 0.5 0.2
|
||||
b_st1[25] 0.5 0.2
|
||||
b_st1[26] 0.5 0.2
|
||||
b_st1[27] 0.5 0.2
|
||||
b_st1[28] 0.5 0.2
|
||||
b_st1[29] 0.5 0.2
|
||||
b_st1[30] 0.5 0.2
|
||||
q[0] 0.5 0.2
|
||||
q[1] 0.5 0.2
|
||||
q[2] 0.5 0.2
|
||||
q[3] 0.5 0.2
|
||||
q[4] 0.5 0.2
|
||||
q[5] 0.5 0.2
|
||||
q[6] 0.5 0.2
|
||||
q[7] 0.5 0.2
|
||||
q[8] 0.5 0.2
|
||||
q[9] 0.5 0.2
|
||||
q[10] 0.5 0.2
|
||||
q[11] 0.5 0.2
|
||||
q[12] 0.5 0.2
|
||||
q[13] 0.5 0.2
|
||||
q[14] 0.5 0.2
|
||||
q[15] 0.5 0.2
|
||||
q[16] 0.5 0.2
|
||||
q[17] 0.5 0.2
|
||||
q[18] 0.5 0.2
|
||||
q[19] 0.5 0.2
|
||||
q[20] 0.5 0.2
|
||||
q[21] 0.5 0.2
|
||||
q[22] 0.5 0.2
|
||||
q[23] 0.5 0.2
|
||||
q[24] 0.5 0.2
|
||||
q[25] 0.5 0.2
|
||||
q[26] 0.5 0.2
|
||||
q[27] 0.5 0.2
|
||||
q[28] 0.5 0.2
|
||||
q[29] 0.5 0.2
|
||||
q[30] 0.5 0.2
|
||||
q[31] 0.5 0.2
|
||||
AplusB[0] 0.5 0.2
|
||||
AplusB[1] 0.5 0.2
|
||||
AplusB[2] 0.5 0.2
|
||||
AplusB[3] 0.5 0.2
|
||||
AplusB[4] 0.5 0.2
|
||||
AplusB[5] 0.5 0.2
|
||||
AplusB[6] 0.5 0.2
|
||||
AplusB[7] 0.5 0.2
|
||||
AplusB[8] 0.5 0.2
|
||||
AplusB[9] 0.5 0.2
|
||||
AplusB[10] 0.5 0.2
|
||||
AplusB[11] 0.5 0.2
|
||||
AplusB[12] 0.5 0.2
|
||||
AplusB[13] 0.5 0.2
|
||||
AplusB[14] 0.5 0.2
|
||||
AplusB[15] 0.5 0.2
|
||||
AplusB[16] 0.5 0.2
|
||||
AplusB[17] 0.5 0.2
|
||||
AplusB[18] 0.5 0.2
|
||||
AplusB[19] 0.5 0.2
|
||||
AplusB[20] 0.5 0.2
|
||||
AplusB[21] 0.5 0.2
|
||||
AplusB[22] 0.5 0.2
|
||||
AplusB[23] 0.5 0.2
|
||||
AplusB[24] 0.5 0.2
|
||||
AplusB[25] 0.5 0.2
|
||||
AplusB[26] 0.5 0.2
|
||||
AplusB[27] 0.5 0.2
|
||||
AplusB[28] 0.5 0.2
|
||||
AplusB[29] 0.5 0.2
|
||||
AplusB[30] 0.5 0.2
|
||||
AplusB[31] 0.5 0.2
|
||||
cint01 0.5 0.2
|
||||
cint02 0.5 0.2
|
||||
cint03 0.5 0.2
|
||||
cint04 0.5 0.2
|
||||
cint05 0.5 0.2
|
||||
cint06 0.5 0.2
|
||||
cint07 0.5 0.2
|
||||
cint08 0.5 0.2
|
||||
cint09 0.5 0.2
|
||||
cint10 0.5 0.2
|
||||
cint11 0.5 0.2
|
||||
cint12 0.5 0.2
|
||||
cint13 0.5 0.2
|
||||
cint14 0.5 0.2
|
||||
cint15 0.5 0.2
|
||||
cint16 0.5 0.2
|
||||
cint17 0.5 0.2
|
||||
cint18 0.5 0.2
|
||||
cint19 0.5 0.2
|
||||
cint20 0.5 0.2
|
||||
cint21 0.5 0.2
|
||||
cint22 0.5 0.2
|
||||
cint23 0.5 0.2
|
||||
cint24 0.5 0.2
|
||||
cint25 0.5 0.2
|
||||
cint26 0.5 0.2
|
||||
cint27 0.5 0.2
|
||||
cint28 0.5 0.2
|
||||
cint29 0.5 0.2
|
||||
cint30 0.5 0.2
|
||||
cint31 0.5 0.2
|
||||
zero00 0 0
|
||||
|
|
@ -1,278 +0,0 @@
|
|||
# Benchmark pipelined_32b_adder
|
||||
.model pipelined_32b_adder
|
||||
.inputs clk wen ren \
|
||||
raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
|
||||
waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \
|
||||
a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] \
|
||||
a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] \
|
||||
a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] \
|
||||
b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] \
|
||||
b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] \
|
||||
b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30]
|
||||
.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] q[8] q[9] q[10] \
|
||||
q[11] q[12] q[13] q[14] q[15] q[16] q[17] q[18] q[19] q[20] \
|
||||
q[21] q[22] q[23] q[24] q[25] q[26] q[27] q[28] q[29] q[30] q[31]
|
||||
|
||||
# Start pipeline
|
||||
# Pipeline a
|
||||
.subckt shift D=a[0] clk=clk Q=a_st0[0]
|
||||
.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
|
||||
.subckt shift D=a[1] clk=clk Q=a_st0[1]
|
||||
.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
|
||||
.subckt shift D=a[2] clk=clk Q=a_st0[2]
|
||||
.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
|
||||
.subckt shift D=a[3] clk=clk Q=a_st0[3]
|
||||
.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
|
||||
.subckt shift D=a[4] clk=clk Q=a_st0[4]
|
||||
.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
|
||||
.subckt shift D=a[5] clk=clk Q=a_st0[5]
|
||||
.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
|
||||
.subckt shift D=a[6] clk=clk Q=a_st0[6]
|
||||
.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]
|
||||
.subckt shift D=a[7] clk=clk Q=a_st0[7]
|
||||
.subckt shift D=a_st0[7] clk=clk Q=a_st1[7]
|
||||
.subckt shift D=a[8] clk=clk Q=a_st0[8]
|
||||
.subckt shift D=a_st0[8] clk=clk Q=a_st1[8]
|
||||
.subckt shift D=a[9] clk=clk Q=a_st0[9]
|
||||
.subckt shift D=a_st0[9] clk=clk Q=a_st1[9]
|
||||
.subckt shift D=a[10] clk=clk Q=a_st0[10]
|
||||
.subckt shift D=a_st0[10] clk=clk Q=a_st1[10]
|
||||
.subckt shift D=a[11] clk=clk Q=a_st0[11]
|
||||
.subckt shift D=a_st0[11] clk=clk Q=a_st1[11]
|
||||
.subckt shift D=a[12] clk=clk Q=a_st0[12]
|
||||
.subckt shift D=a_st0[12] clk=clk Q=a_st1[12]
|
||||
.subckt shift D=a[13] clk=clk Q=a_st0[13]
|
||||
.subckt shift D=a_st0[13] clk=clk Q=a_st1[13]
|
||||
.subckt shift D=a[14] clk=clk Q=a_st0[14]
|
||||
.subckt shift D=a_st0[14] clk=clk Q=a_st1[14]
|
||||
.subckt shift D=a[15] clk=clk Q=a_st0[15]
|
||||
.subckt shift D=a_st0[15] clk=clk Q=a_st1[15]
|
||||
.subckt shift D=a[16] clk=clk Q=a_st0[16]
|
||||
.subckt shift D=a_st0[16] clk=clk Q=a_st1[16]
|
||||
.subckt shift D=a[17] clk=clk Q=a_st0[17]
|
||||
.subckt shift D=a_st0[17] clk=clk Q=a_st1[17]
|
||||
.subckt shift D=a[18] clk=clk Q=a_st0[18]
|
||||
.subckt shift D=a_st0[18] clk=clk Q=a_st1[18]
|
||||
.subckt shift D=a[19] clk=clk Q=a_st0[19]
|
||||
.subckt shift D=a_st0[19] clk=clk Q=a_st1[19]
|
||||
.subckt shift D=a[20] clk=clk Q=a_st0[20]
|
||||
.subckt shift D=a_st0[20] clk=clk Q=a_st1[20]
|
||||
.subckt shift D=a[21] clk=clk Q=a_st0[21]
|
||||
.subckt shift D=a_st0[21] clk=clk Q=a_st1[21]
|
||||
.subckt shift D=a[22] clk=clk Q=a_st0[22]
|
||||
.subckt shift D=a_st0[22] clk=clk Q=a_st1[22]
|
||||
.subckt shift D=a[23] clk=clk Q=a_st0[23]
|
||||
.subckt shift D=a_st0[23] clk=clk Q=a_st1[23]
|
||||
.subckt shift D=a[24] clk=clk Q=a_st0[24]
|
||||
.subckt shift D=a_st0[24] clk=clk Q=a_st1[24]
|
||||
.subckt shift D=a[25] clk=clk Q=a_st0[25]
|
||||
.subckt shift D=a_st0[25] clk=clk Q=a_st1[25]
|
||||
.subckt shift D=a[26] clk=clk Q=a_st0[26]
|
||||
.subckt shift D=a_st0[26] clk=clk Q=a_st1[26]
|
||||
.subckt shift D=a[27] clk=clk Q=a_st0[27]
|
||||
.subckt shift D=a_st0[27] clk=clk Q=a_st1[27]
|
||||
.subckt shift D=a[28] clk=clk Q=a_st0[28]
|
||||
.subckt shift D=a_st0[28] clk=clk Q=a_st1[28]
|
||||
.subckt shift D=a[29] clk=clk Q=a_st0[29]
|
||||
.subckt shift D=a_st0[29] clk=clk Q=a_st1[29]
|
||||
.subckt shift D=a[30] clk=clk Q=a_st0[30]
|
||||
.subckt shift D=a_st0[30] clk=clk Q=a_st1[30]
|
||||
|
||||
# Pipeline b
|
||||
.subckt shift D=b[0] clk=clk Q=b_st0[0]
|
||||
.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
|
||||
.subckt shift D=b[1] clk=clk Q=b_st0[1]
|
||||
.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
|
||||
.subckt shift D=b[2] clk=clk Q=b_st0[2]
|
||||
.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
|
||||
.subckt shift D=b[3] clk=clk Q=b_st0[3]
|
||||
.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
|
||||
.subckt shift D=b[4] clk=clk Q=b_st0[4]
|
||||
.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
|
||||
.subckt shift D=b[5] clk=clk Q=b_st0[5]
|
||||
.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
|
||||
.subckt shift D=b[6] clk=clk Q=b_st0[6]
|
||||
.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]
|
||||
.subckt shift D=b[7] clk=clk Q=b_st0[7]
|
||||
.subckt shift D=b_st0[7] clk=clk Q=b_st1[7]
|
||||
.subckt shift D=b[8] clk=clk Q=b_st0[8]
|
||||
.subckt shift D=b_st0[8] clk=clk Q=b_st1[8]
|
||||
.subckt shift D=b[9] clk=clk Q=b_st0[9]
|
||||
.subckt shift D=b_st0[9] clk=clk Q=b_st1[9]
|
||||
.subckt shift D=b[10] clk=clk Q=b_st0[10]
|
||||
.subckt shift D=b_st0[10] clk=clk Q=b_st1[10]
|
||||
.subckt shift D=b[11] clk=clk Q=b_st0[11]
|
||||
.subckt shift D=b_st0[11] clk=clk Q=b_st1[11]
|
||||
.subckt shift D=b[12] clk=clk Q=b_st0[12]
|
||||
.subckt shift D=b_st0[12] clk=clk Q=b_st1[12]
|
||||
.subckt shift D=b[13] clk=clk Q=b_st0[13]
|
||||
.subckt shift D=b_st0[13] clk=clk Q=b_st1[13]
|
||||
.subckt shift D=b[14] clk=clk Q=b_st0[14]
|
||||
.subckt shift D=b_st0[14] clk=clk Q=b_st1[14]
|
||||
.subckt shift D=b[15] clk=clk Q=b_st0[15]
|
||||
.subckt shift D=b_st0[15] clk=clk Q=b_st1[15]
|
||||
.subckt shift D=b[16] clk=clk Q=b_st0[16]
|
||||
.subckt shift D=b_st0[16] clk=clk Q=b_st1[16]
|
||||
.subckt shift D=b[17] clk=clk Q=b_st0[17]
|
||||
.subckt shift D=b_st0[17] clk=clk Q=b_st1[17]
|
||||
.subckt shift D=b[18] clk=clk Q=b_st0[18]
|
||||
.subckt shift D=b_st0[18] clk=clk Q=b_st1[18]
|
||||
.subckt shift D=b[19] clk=clk Q=b_st0[19]
|
||||
.subckt shift D=b_st0[19] clk=clk Q=b_st1[19]
|
||||
.subckt shift D=b[20] clk=clk Q=b_st0[20]
|
||||
.subckt shift D=b_st0[20] clk=clk Q=b_st1[20]
|
||||
.subckt shift D=b[21] clk=clk Q=b_st0[21]
|
||||
.subckt shift D=b_st0[21] clk=clk Q=b_st1[21]
|
||||
.subckt shift D=b[22] clk=clk Q=b_st0[22]
|
||||
.subckt shift D=b_st0[22] clk=clk Q=b_st1[22]
|
||||
.subckt shift D=b[23] clk=clk Q=b_st0[23]
|
||||
.subckt shift D=b_st0[23] clk=clk Q=b_st1[23]
|
||||
.subckt shift D=b[24] clk=clk Q=b_st0[24]
|
||||
.subckt shift D=b_st0[24] clk=clk Q=b_st1[24]
|
||||
.subckt shift D=b[25] clk=clk Q=b_st0[25]
|
||||
.subckt shift D=b_st0[25] clk=clk Q=b_st1[25]
|
||||
.subckt shift D=b[26] clk=clk Q=b_st0[26]
|
||||
.subckt shift D=b_st0[26] clk=clk Q=b_st1[26]
|
||||
.subckt shift D=b[27] clk=clk Q=b_st0[27]
|
||||
.subckt shift D=b_st0[27] clk=clk Q=b_st1[27]
|
||||
.subckt shift D=b[28] clk=clk Q=b_st0[28]
|
||||
.subckt shift D=b_st0[28] clk=clk Q=b_st1[28]
|
||||
.subckt shift D=b[29] clk=clk Q=b_st0[29]
|
||||
.subckt shift D=b_st0[29] clk=clk Q=b_st1[29]
|
||||
.subckt shift D=b[30] clk=clk Q=b_st0[30]
|
||||
.subckt shift D=b_st0[30] clk=clk Q=b_st1[30]
|
||||
|
||||
# Pipeline waddr
|
||||
.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
|
||||
.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0]
|
||||
.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1]
|
||||
.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1]
|
||||
.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2]
|
||||
.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2]
|
||||
.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3]
|
||||
.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3]
|
||||
.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4]
|
||||
.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
|
||||
.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
|
||||
.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
|
||||
.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6]
|
||||
.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6]
|
||||
.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7]
|
||||
.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7]
|
||||
.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8]
|
||||
.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8]
|
||||
.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9]
|
||||
.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9]
|
||||
.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10]
|
||||
.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10]
|
||||
|
||||
# Pipeline wen
|
||||
.subckt shift D=wen clk=clk Q=wen_st0
|
||||
.subckt shift D=wen_st0 clk=clk Q=wen_st1
|
||||
# End pipeline
|
||||
|
||||
# Start adder
|
||||
.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
|
||||
.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
|
||||
.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
|
||||
.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
|
||||
.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
|
||||
.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
|
||||
.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
|
||||
.subckt adder a=a_st1[7] b=b_st1[7] cin=cint07 cout=cint08 sumout=AplusB[7]
|
||||
.subckt adder a=a_st1[8] b=b_st1[8] cin=cint08 cout=cint09 sumout=AplusB[8]
|
||||
.subckt adder a=a_st1[9] b=b_st1[9] cin=cint09 cout=cint10 sumout=AplusB[9]
|
||||
.subckt adder a=a_st1[10] b=b_st1[10] cin=cint10 cout=cint11 sumout=AplusB[10]
|
||||
.subckt adder a=a_st1[11] b=b_st1[11] cin=cint11 cout=cint12 sumout=AplusB[11]
|
||||
.subckt adder a=a_st1[12] b=b_st1[12] cin=cint12 cout=cint13 sumout=AplusB[12]
|
||||
.subckt adder a=a_st1[13] b=b_st1[13] cin=cint13 cout=cint14 sumout=AplusB[13]
|
||||
.subckt adder a=a_st1[14] b=b_st1[14] cin=cint14 cout=cint15 sumout=AplusB[14]
|
||||
.subckt adder a=a_st1[15] b=b_st1[15] cin=cint15 cout=cint16 sumout=AplusB[15]
|
||||
.subckt adder a=a_st1[16] b=b_st1[16] cin=cint16 cout=cint17 sumout=AplusB[16]
|
||||
.subckt adder a=a_st1[17] b=b_st1[17] cin=cint17 cout=cint18 sumout=AplusB[17]
|
||||
.subckt adder a=a_st1[18] b=b_st1[18] cin=cint18 cout=cint19 sumout=AplusB[18]
|
||||
.subckt adder a=a_st1[19] b=b_st1[19] cin=cint19 cout=cint20 sumout=AplusB[19]
|
||||
.subckt adder a=a_st1[20] b=b_st1[20] cin=cint20 cout=cint21 sumout=AplusB[20]
|
||||
.subckt adder a=a_st1[21] b=b_st1[21] cin=cint21 cout=cint22 sumout=AplusB[21]
|
||||
.subckt adder a=a_st1[22] b=b_st1[22] cin=cint22 cout=cint23 sumout=AplusB[22]
|
||||
.subckt adder a=a_st1[23] b=b_st1[23] cin=cint23 cout=cint24 sumout=AplusB[23]
|
||||
.subckt adder a=a_st1[24] b=b_st1[24] cin=cint24 cout=cint25 sumout=AplusB[24]
|
||||
.subckt adder a=a_st1[25] b=b_st1[25] cin=cint25 cout=cint26 sumout=AplusB[25]
|
||||
.subckt adder a=a_st1[26] b=b_st1[26] cin=cint26 cout=cint27 sumout=AplusB[26]
|
||||
.subckt adder a=a_st1[27] b=b_st1[27] cin=cint27 cout=cint28 sumout=AplusB[27]
|
||||
.subckt adder a=a_st1[28] b=b_st1[28] cin=cint28 cout=cint29 sumout=AplusB[28]
|
||||
.subckt adder a=a_st1[29] b=b_st1[29] cin=cint29 cout=cint30 sumout=AplusB[29]
|
||||
.subckt adder a=a_st1[30] b=b_st1[30] cin=cint30 cout=cint31 sumout=AplusB[30]
|
||||
.subckt adder a=zero00 b=zero00 cin=cint31 cout=unconn sumout=AplusB[31]
|
||||
# End adder
|
||||
|
||||
# Start DPRAM
|
||||
.subckt dpram clk=clk wen=wen_st1 ren=ren \
|
||||
waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
|
||||
waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \
|
||||
raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
|
||||
raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \
|
||||
d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
|
||||
d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=AplusB[8] d_in[9]=AplusB[9] d_in[10]=AplusB[10] d_in[11]=AplusB[11] \
|
||||
d_in[12]=AplusB[12] d_in[13]=AplusB[13] d_in[14]=AplusB[14] d_in[15]=AplusB[15] d_in[16]=AplusB[16] d_in[17]=AplusB[17] \
|
||||
d_in[18]=AplusB[18] d_in[19]=AplusB[19] d_in[20]=AplusB[20] d_in[21]=AplusB[21] d_in[22]=AplusB[22] d_in[23]=AplusB[23] \
|
||||
d_in[24]=AplusB[24] d_in[25]=AplusB[25] d_in[26]=AplusB[26] d_in[27]=AplusB[27] d_in[28]=AplusB[28] d_in[29]=AplusB[29] \
|
||||
d_in[30]=AplusB[30] d_in[31]=AplusB[31] \
|
||||
d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
|
||||
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
|
||||
d_out[6]=q[6] d_out[7]=q[7] d_out[8]=q[8] d_out[9]=q[9] d_out[10]=q[10] \
|
||||
d_out[11]=q[11] d_out[12]=q[12] d_out[13]=q[13] d_out[14]=q[14] d_out[15]=q[15] \
|
||||
d_out[16]=q[16] d_out[17]=q[17] d_out[18]=q[18] d_out[19]=q[19] d_out[20]=q[20] \
|
||||
d_out[21]=q[21] d_out[22]=q[22] d_out[23]=q[23] d_out[24]=q[24] d_out[25]=q[25] \
|
||||
d_out[26]=q[26] d_out[27]=q[27] d_out[28]=q[28] d_out[29]=q[29] d_out[30]=q[30] d_out[31]=q[31] \
|
||||
d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn
|
||||
# End DPRAM
|
||||
|
||||
# Start global variable
|
||||
.names zero00
|
||||
0
|
||||
# End global variable
|
||||
|
||||
|
||||
.end
|
||||
|
||||
# Start blackbox definition
|
||||
.model dpram
|
||||
.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \
|
||||
waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \
|
||||
raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
|
||||
d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \
|
||||
d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \
|
||||
d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \
|
||||
d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \
|
||||
d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \
|
||||
d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \
|
||||
d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \
|
||||
d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63]
|
||||
.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \
|
||||
d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \
|
||||
d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \
|
||||
d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \
|
||||
d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \
|
||||
d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \
|
||||
d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \
|
||||
d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \
|
||||
d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \
|
||||
d_out[63]
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model adder
|
||||
.inputs a b cin
|
||||
.outputs cout sumout
|
||||
.blackbox
|
||||
.end
|
||||
|
||||
|
||||
.model shift
|
||||
.inputs D clk
|
||||
.outputs Q
|
||||
.blackbox
|
||||
.end
|
||||
# End blackbox definition
|
||||
|
|
@ -1,156 +0,0 @@
|
|||
/////////////////////////////////////
|
||||
// //
|
||||
// ERI summit demo-benchmark //
|
||||
// pipelined_32b_adder_tb //
|
||||
// by Aurelien //
|
||||
// //
|
||||
/////////////////////////////////////
|
||||
|
||||
`timescale 1 ns/ 1 ps
|
||||
|
||||
module pipelined_32b_adder_ERI_demo_tb();
|
||||
reg clk;
|
||||
reg[10:0] raddr;
|
||||
reg[10:0] waddr;
|
||||
reg ren;
|
||||
reg wen;
|
||||
reg[30:0] a;
|
||||
reg[30:0] b;
|
||||
wire[31:0] q_gfpga;
|
||||
wire[31:0] q_bench;
|
||||
reg[31:0] q_flag;
|
||||
|
||||
pipelined_32b_adder_top_formal_verification DUT(
|
||||
.clk_fm (clk),
|
||||
.raddr_0_fm (raddr[0]),
|
||||
.raddr_1_fm (raddr[1]),
|
||||
.raddr_2_fm (raddr[2]),
|
||||
.raddr_3_fm (raddr[3]),
|
||||
.raddr_4_fm (raddr[4]),
|
||||
.raddr_5_fm (raddr[5]),
|
||||
.raddr_6_fm (raddr[6]),
|
||||
.raddr_7_fm (raddr[7]),
|
||||
.raddr_8_fm (raddr[8]),
|
||||
.raddr_9_fm (raddr[9]),
|
||||
.raddr_10_fm (raddr[10]),
|
||||
.waddr_0_fm (waddr[0]),
|
||||
.waddr_1_fm (waddr[1]),
|
||||
.waddr_2_fm (waddr[2]),
|
||||
.waddr_3_fm (waddr[3]),
|
||||
.waddr_4_fm (waddr[4]),
|
||||
.waddr_5_fm (waddr[5]),
|
||||
.waddr_6_fm (waddr[6]),
|
||||
.waddr_7_fm (waddr[7]),
|
||||
.waddr_8_fm (waddr[8]),
|
||||
.waddr_9_fm (waddr[9]),
|
||||
.waddr_10_fm (waddr[10]),
|
||||
.ren_fm (ren),
|
||||
.wen_fm (wen),
|
||||
.a_0_fm (a[0]),
|
||||
.a_1_fm (a[1]),
|
||||
.a_2_fm (a[2]),
|
||||
.a_3_fm (a[3]),
|
||||
.a_4_fm (a[4]),
|
||||
.a_5_fm (a[5]),
|
||||
.a_6_fm (a[6]),
|
||||
.a_7_fm (a[7]),
|
||||
.a_8_fm (a[8]),
|
||||
.a_9_fm (a[9]),
|
||||
.a_10_fm (a[10]),
|
||||
.a_11_fm (a[11]),
|
||||
.a_12_fm (a[12]),
|
||||
.a_13_fm (a[13]),
|
||||
.a_14_fm (a[14]),
|
||||
.a_15_fm (a[15]),
|
||||
.a_16_fm (a[16]),
|
||||
.a_17_fm (a[17]),
|
||||
.a_18_fm (a[18]),
|
||||
.a_19_fm (a[19]),
|
||||
.a_20_fm (a[20]),
|
||||
.a_21_fm (a[21]),
|
||||
.a_22_fm (a[22]),
|
||||
.a_23_fm (a[23]),
|
||||
.a_24_fm (a[24]),
|
||||
.a_25_fm (a[25]),
|
||||
.a_26_fm (a[26]),
|
||||
.a_27_fm (a[27]),
|
||||
.a_28_fm (a[28]),
|
||||
.a_29_fm (a[29]),
|
||||
.a_30_fm (a[30]),
|
||||
.b_0_fm (b[0]),
|
||||
.b_1_fm (b[1]),
|
||||
.b_2_fm (b[2]),
|
||||
.b_3_fm (b[3]),
|
||||
.b_4_fm (b[4]),
|
||||
.b_5_fm (b[5]),
|
||||
.b_6_fm (b[6]),
|
||||
.b_7_fm (b[7]),
|
||||
.b_8_fm (b[8]),
|
||||
.b_9_fm (b[9]),
|
||||
.b_10_fm (b[10]),
|
||||
.b_11_fm (b[11]),
|
||||
.b_12_fm (b[12]),
|
||||
.b_13_fm (b[13]),
|
||||
.b_14_fm (b[14]),
|
||||
.b_15_fm (b[15]),
|
||||
.b_16_fm (b[16]),
|
||||
.b_17_fm (b[17]),
|
||||
.b_18_fm (b[18]),
|
||||
.b_19_fm (b[19]),
|
||||
.b_20_fm (b[20]),
|
||||
.b_21_fm (b[21]),
|
||||
.b_22_fm (b[22]),
|
||||
.b_23_fm (b[23]),
|
||||
.b_24_fm (b[24]),
|
||||
.b_25_fm (b[25]),
|
||||
.b_26_fm (b[26]),
|
||||
.b_27_fm (b[27]),
|
||||
.b_28_fm (b[28]),
|
||||
.b_29_fm (b[29]),
|
||||
.b_30_fm (b[30]),
|
||||
.out_q_0_fm (q_gfpga[0]),
|
||||
.out_q_1_fm (q_gfpga[1]),
|
||||
.out_q_2_fm (q_gfpga[2]),
|
||||
.out_q_3_fm (q_gfpga[3]),
|
||||
.out_q_4_fm (q_gfpga[4]),
|
||||
.out_q_5_fm (q_gfpga[5]),
|
||||
.out_q_6_fm (q_gfpga[6]),
|
||||
.out_q_7_fm (q_gfpga[7]),
|
||||
.out_q_8_fm (q_gfpga[8]),
|
||||
.out_q_9_fm (q_gfpga[9]),
|
||||
.out_q_10_fm (q_gfpga[10]),
|
||||
.out_q_11_fm (q_gfpga[11]),
|
||||
.out_q_12_fm (q_gfpga[12]),
|
||||
.out_q_13_fm (q_gfpga[13]),
|
||||
.out_q_14_fm (q_gfpga[14]),
|
||||
.out_q_15_fm (q_gfpga[15]),
|
||||
.out_q_16_fm (q_gfpga[16]),
|
||||
.out_q_17_fm (q_gfpga[17]),
|
||||
.out_q_18_fm (q_gfpga[18]),
|
||||
.out_q_19_fm (q_gfpga[19]),
|
||||
.out_q_20_fm (q_gfpga[20]),
|
||||
.out_q_21_fm (q_gfpga[21]),
|
||||
.out_q_22_fm (q_gfpga[22]),
|
||||
.out_q_23_fm (q_gfpga[23]),
|
||||
.out_q_24_fm (q_gfpga[24]),
|
||||
.out_q_25_fm (q_gfpga[25]),
|
||||
.out_q_26_fm (q_gfpga[26]),
|
||||
.out_q_27_fm (q_gfpga[27]),
|
||||
.out_q_28_fm (q_gfpga[28]),
|
||||
.out_q_29_fm (q_gfpga[29]),
|
||||
.out_q_30_fm (q_gfpga[30]),
|
||||
.out_q_31_fm (q_gfpga[31])
|
||||
);
|
||||
|
||||
pipelined_32b_adder ref0(
|
||||
.clk (clk),
|
||||
.raddr (raddr),
|
||||
.waddr (waddr),
|
||||
.ren (ren),
|
||||
.wen (wen),
|
||||
.a (a),
|
||||
.b (b),
|
||||
.q (q_bench)
|
||||
);
|
||||
|
||||
endmodule : pipelined_32b_adder_ERI_demo_tb
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
clk 0.5 0.2
|
||||
wen 0.5 0.2
|
||||
wen_st0 0.5 0.2
|
||||
wen_st1 0.5 0.2
|
||||
ren 0.5 0.2
|
||||
raddr[0] 0.5 0.2
|
||||
raddr[1] 0.5 0.2
|
||||
raddr[2] 0.5 0.2
|
||||
raddr[3] 0.5 0.2
|
||||
raddr[4] 0.5 0.2
|
||||
raddr[5] 0.5 0.2
|
||||
waddr[0] 0.5 0.2
|
||||
waddr[1] 0.5 0.2
|
||||
waddr[2] 0.5 0.2
|
||||
waddr[3] 0.5 0.2
|
||||
waddr[4] 0.5 0.2
|
||||
waddr[5] 0.5 0.2
|
||||
waddr_st0[0] 0.5 0.2
|
||||
waddr_st0[1] 0.5 0.2
|
||||
waddr_st0[2] 0.5 0.2
|
||||
waddr_st0[3] 0.5 0.2
|
||||
waddr_st0[4] 0.5 0.2
|
||||
waddr_st0[5] 0.5 0.2
|
||||
waddr_st1[0] 0.5 0.2
|
||||
waddr_st1[1] 0.5 0.2
|
||||
waddr_st1[2] 0.5 0.2
|
||||
waddr_st1[3] 0.5 0.2
|
||||
waddr_st1[4] 0.5 0.2
|
||||
waddr_st1[5] 0.5 0.2
|
||||
a[0] 0.5 0.2
|
||||
a[1] 0.5 0.2
|
||||
a[2] 0.5 0.2
|
||||
a[3] 0.5 0.2
|
||||
a[4] 0.5 0.2
|
||||
a[5] 0.5 0.2
|
||||
a[6] 0.5 0.2
|
||||
a_st0[0] 0.5 0.2
|
||||
a_st0[1] 0.5 0.2
|
||||
a_st0[2] 0.5 0.2
|
||||
a_st0[3] 0.5 0.2
|
||||
a_st0[4] 0.5 0.2
|
||||
a_st0[5] 0.5 0.2
|
||||
a_st0[6] 0.5 0.2
|
||||
a_st1[0] 0.5 0.2
|
||||
a_st1[1] 0.5 0.2
|
||||
a_st1[2] 0.5 0.2
|
||||
a_st1[3] 0.5 0.2
|
||||
a_st1[4] 0.5 0.2
|
||||
a_st1[5] 0.5 0.2
|
||||
a_st1[6] 0.5 0.2
|
||||
b[0] 0.5 0.2
|
||||
b[1] 0.5 0.2
|
||||
b[2] 0.5 0.2
|
||||
b[3] 0.5 0.2
|
||||
b[4] 0.5 0.2
|
||||
b[5] 0.5 0.2
|
||||
b[6] 0.5 0.2
|
||||
b_st0[0] 0.5 0.2
|
||||
b_st0[1] 0.5 0.2
|
||||
b_st0[2] 0.5 0.2
|
||||
b_st0[3] 0.5 0.2
|
||||
b_st0[4] 0.5 0.2
|
||||
b_st0[5] 0.5 0.2
|
||||
b_st0[6] 0.5 0.2
|
||||
b_st1[0] 0.5 0.2
|
||||
b_st1[1] 0.5 0.2
|
||||
b_st1[2] 0.5 0.2
|
||||
b_st1[3] 0.5 0.2
|
||||
b_st1[4] 0.5 0.2
|
||||
b_st1[5] 0.5 0.2
|
||||
b_st1[6] 0.5 0.2
|
||||
q[0] 0.5 0.2
|
||||
q[1] 0.5 0.2
|
||||
q[2] 0.5 0.2
|
||||
q[3] 0.5 0.2
|
||||
q[4] 0.5 0.2
|
||||
q[5] 0.5 0.2
|
||||
q[6] 0.5 0.2
|
||||
q[7] 0.5 0.2
|
||||
AplusB[0] 0.5 0.2
|
||||
AplusB[1] 0.5 0.2
|
||||
AplusB[2] 0.5 0.2
|
||||
AplusB[3] 0.5 0.2
|
||||
AplusB[4] 0.5 0.2
|
||||
AplusB[5] 0.5 0.2
|
||||
AplusB[6] 0.5 0.2
|
||||
AplusB[7] 0.5 0.2
|
||||
cint01 0.5 0.2
|
||||
cint02 0.5 0.2
|
||||
cint03 0.5 0.2
|
||||
cint04 0.5 0.2
|
||||
cint05 0.5 0.2
|
||||
cint06 0.5 0.2
|
||||
cint07 0.5 0.2
|
||||
zero00 0 0
|
||||
|
|
@ -1,50 +1,40 @@
|
|||
# Benchmark pipelined_32b_adder
|
||||
.model pipelined_32b_adder
|
||||
.inputs clk wen ren \
|
||||
raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \
|
||||
waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \
|
||||
a[0] b[0]
|
||||
.outputs q[0] q[1]
|
||||
|
||||
# Pipeline with #.latch
|
||||
#.latch a[0] a_st0[0] re clk 0
|
||||
#.latch a_st0[0] a_st1[0] re clk 0
|
||||
#.latch b[0] b_st0[0] re clk 0
|
||||
#.latch b_st0[0] b_st1[0] re clk 0
|
||||
#.latch wen wen_st0 re clk 0
|
||||
#.latch wen_st0 wen_st1 re clk 0
|
||||
#.latch waddr[0] waddr_st0[0] re clk 0
|
||||
#.latch waddr_st0[0] waddr_st1[0] re clk 0
|
||||
#.latch waddr[1] waddr_st0[1] re clk 0
|
||||
#.latch waddr_st0[1] waddr_st1[1] re clk 0
|
||||
#.latch waddr[2] waddr_st0[2] re clk 0
|
||||
#.latch waddr_st0[2] waddr_st1[2] re clk 0
|
||||
#.latch waddr[3] waddr_st0[3] re clk 0
|
||||
#.latch waddr_st0[3] waddr_st1[3] re clk 0
|
||||
#.latch waddr[4] waddr_st0[4] re clk 0
|
||||
#.latch waddr_st0[4] waddr_st1[4] re clk 0
|
||||
#.latch waddr[5] waddr_st0[5] re clk 0
|
||||
#.latch waddr_st0[5] waddr_st1[5] re clk 0
|
||||
#.latch waddr[6] waddr_st0[6] re clk 0
|
||||
#.latch waddr_st0[6] waddr_st1[6] re clk 0
|
||||
#.latch waddr[7] waddr_st0[7] re clk 0
|
||||
#.latch waddr_st0[7] waddr_st1[7] re clk 0
|
||||
#.latch waddr[8] waddr_st0[8] re clk 0
|
||||
#.latch waddr_st0[8] waddr_st1[8] re clk 0
|
||||
#.latch waddr[9] waddr_st0[9] re clk 0
|
||||
#.latch waddr_st0[9] waddr_st1[9] re clk 0
|
||||
#.latch waddr[10] waddr_st0[10] re clk 0
|
||||
#.latch waddr_st0[10] waddr_st1[10] re clk 0
|
||||
# End pipeline with #.latch
|
||||
.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6]
|
||||
.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7]
|
||||
|
||||
# Start pipeline
|
||||
# Pipeline a
|
||||
.subckt shift D=a[0] clk=clk Q=a_st0[0]
|
||||
.subckt shift D=a_st0[0] clk=clk Q=a_st1[0]
|
||||
.subckt shift D=a[1] clk=clk Q=a_st0[1]
|
||||
.subckt shift D=a_st0[1] clk=clk Q=a_st1[1]
|
||||
.subckt shift D=a[2] clk=clk Q=a_st0[2]
|
||||
.subckt shift D=a_st0[2] clk=clk Q=a_st1[2]
|
||||
.subckt shift D=a[3] clk=clk Q=a_st0[3]
|
||||
.subckt shift D=a_st0[3] clk=clk Q=a_st1[3]
|
||||
.subckt shift D=a[4] clk=clk Q=a_st0[4]
|
||||
.subckt shift D=a_st0[4] clk=clk Q=a_st1[4]
|
||||
.subckt shift D=a[5] clk=clk Q=a_st0[5]
|
||||
.subckt shift D=a_st0[5] clk=clk Q=a_st1[5]
|
||||
.subckt shift D=a[6] clk=clk Q=a_st0[6]
|
||||
.subckt shift D=a_st0[6] clk=clk Q=a_st1[6]
|
||||
|
||||
# Pipeline b
|
||||
.subckt shift D=b[0] clk=clk Q=b_st0[0]
|
||||
.subckt shift D=b_st0[0] clk=clk Q=b_st1[0]
|
||||
.subckt shift D=b[1] clk=clk Q=b_st0[1]
|
||||
.subckt shift D=b_st0[1] clk=clk Q=b_st1[1]
|
||||
.subckt shift D=b[2] clk=clk Q=b_st0[2]
|
||||
.subckt shift D=b_st0[2] clk=clk Q=b_st1[2]
|
||||
.subckt shift D=b[3] clk=clk Q=b_st0[3]
|
||||
.subckt shift D=b_st0[3] clk=clk Q=b_st1[3]
|
||||
.subckt shift D=b[4] clk=clk Q=b_st0[4]
|
||||
.subckt shift D=b_st0[4] clk=clk Q=b_st1[4]
|
||||
.subckt shift D=b[5] clk=clk Q=b_st0[5]
|
||||
.subckt shift D=b_st0[5] clk=clk Q=b_st1[5]
|
||||
.subckt shift D=b[6] clk=clk Q=b_st0[6]
|
||||
.subckt shift D=b_st0[6] clk=clk Q=b_st1[6]
|
||||
|
||||
# Pipeline waddr
|
||||
.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0]
|
||||
|
|
@ -59,17 +49,6 @@
|
|||
.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4]
|
||||
.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5]
|
||||
.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5]
|
||||
.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6]
|
||||
.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6]
|
||||
.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7]
|
||||
.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7]
|
||||
.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8]
|
||||
.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8]
|
||||
.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9]
|
||||
.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9]
|
||||
.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10]
|
||||
.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10]
|
||||
|
||||
# Pipeline wen
|
||||
.subckt shift D=wen clk=clk Q=wen_st0
|
||||
.subckt shift D=wen_st0 clk=clk Q=wen_st1
|
||||
|
|
@ -77,24 +56,30 @@
|
|||
|
||||
# Start adder
|
||||
.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0]
|
||||
.subckt adder a=zero00 b=zero00 cin=cint01 cout=unconn sumout=AplusB[1]
|
||||
.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1]
|
||||
.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2]
|
||||
.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3]
|
||||
.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4]
|
||||
.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5]
|
||||
.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6]
|
||||
.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7]
|
||||
# End adder
|
||||
|
||||
# Start DPRAM
|
||||
.subckt dpram clk=clk wen=wen_st1 ren=ren \
|
||||
waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \
|
||||
waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \
|
||||
waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \
|
||||
raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \
|
||||
raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \
|
||||
d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=zero00 d_in[3]=zero00 d_in[4]=zero00 d_in[5]=zero00 \
|
||||
d_in[6]=zero00 d_in[7]=zero00 d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
|
||||
raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \
|
||||
d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \
|
||||
d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \
|
||||
d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \
|
||||
d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \
|
||||
d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \
|
||||
d_in[30]=zero00 d_in[31]=zero00 \
|
||||
d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \
|
||||
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=unconn d_out[3]=unconn d_out[4]=unconn d_out[5]=unconn \
|
||||
d_out[6]=unconn d_out[7]=unconn d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
|
||||
d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \
|
||||
d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \
|
||||
d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \
|
||||
d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \
|
||||
d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
/////////////////////////////////////
|
||||
// //
|
||||
// ERI summit demo-benchmark //
|
||||
// pipelined_32b_adder.v //
|
||||
// pipelined_8b_adder.v //
|
||||
// by Aurelien //
|
||||
// //
|
||||
/////////////////////////////////////
|
||||
|
||||
`timescale 1 ns/ 1 ps
|
||||
|
||||
module pipelined_32b_adder(
|
||||
module pipelined_8b_adder(
|
||||
clk,
|
||||
raddr,
|
||||
waddr,
|
||||
|
|
@ -19,26 +19,26 @@ module pipelined_32b_adder(
|
|||
q );
|
||||
|
||||
input clk;
|
||||
input[10:0] raddr;
|
||||
input[10:0] waddr;
|
||||
input[5:0] raddr;
|
||||
input[5:0] waddr;
|
||||
input ren;
|
||||
input wen;
|
||||
input[30:0] a;
|
||||
input[30:0] b;
|
||||
output[31:0] q;
|
||||
input[6:0] a;
|
||||
input[6:0] b;
|
||||
output[7:0] q;
|
||||
|
||||
reg[2047:0] ram[31:0];
|
||||
reg[30:0] a_st0;
|
||||
reg[30:0] a_st1;
|
||||
reg[30:0] b_st0;
|
||||
reg[30:0] b_st1;
|
||||
reg[10:0] waddr_st0;
|
||||
reg[10:0] waddr_st1;
|
||||
reg[63:0] ram[7:0];
|
||||
reg[6:0] a_st0;
|
||||
reg[6:0] a_st1;
|
||||
reg[6:0] b_st0;
|
||||
reg[6:0] b_st1;
|
||||
reg[8:0] waddr_st0;
|
||||
reg[8:0] waddr_st1;
|
||||
reg wen_st0;
|
||||
reg wen_st1;
|
||||
reg[31:0] q_int;
|
||||
reg[7:0] q_int;
|
||||
|
||||
wire[31:0] AplusB;
|
||||
wire[7:0] AplusB;
|
||||
|
||||
assign AplusB = a_st1 + b_st1;
|
||||
assign q = q_int;
|
||||
|
|
@ -60,4 +60,4 @@ module pipelined_32b_adder(
|
|||
end
|
||||
end
|
||||
|
||||
endmodule : pipelined_32b_adder
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
`timescale 1 ns/ 100 ps
|
||||
|
||||
`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v"
|
||||
|
||||
module pipelined_8b_adder_top_formal_verification_random_tb();
|
||||
reg clk;
|
||||
reg[5:0] raddr;
|
||||
reg[5:0] waddr;
|
||||
reg ren;
|
||||
reg wen;
|
||||
reg[6:0] a;
|
||||
reg[6:0] b;
|
||||
wire[7:0] q_gfpga;
|
||||
wire[7:0] q_bench;
|
||||
reg[7:0] q_flag;
|
||||
|
||||
pipelined_8b_adder_top_formal_verification DUT(
|
||||
.clk_fm (clk),
|
||||
.raddr_0__fm (raddr[0]),
|
||||
.raddr_1__fm (raddr[1]),
|
||||
.raddr_2__fm (raddr[2]),
|
||||
.raddr_3__fm (raddr[3]),
|
||||
.raddr_4__fm (raddr[4]),
|
||||
.raddr_5__fm (raddr[5]),
|
||||
.waddr_0__fm (waddr[0]),
|
||||
.waddr_1__fm (waddr[1]),
|
||||
.waddr_2__fm (waddr[2]),
|
||||
.waddr_3__fm (waddr[3]),
|
||||
.waddr_4__fm (waddr[4]),
|
||||
.waddr_5__fm (waddr[5]),
|
||||
.ren_fm (ren),
|
||||
.wen_fm (wen),
|
||||
.a_0__fm (a[0]),
|
||||
.a_1__fm (a[1]),
|
||||
.a_2__fm (a[2]),
|
||||
.a_3__fm (a[3]),
|
||||
.a_4__fm (a[4]),
|
||||
.a_5__fm (a[5]),
|
||||
.a_6__fm (a[6]),
|
||||
.b_0__fm (b[0]),
|
||||
.b_1__fm (b[1]),
|
||||
.b_2__fm (b[2]),
|
||||
.b_3__fm (b[3]),
|
||||
.b_4__fm (b[4]),
|
||||
.b_5__fm (b[5]),
|
||||
.b_6__fm (b[6]),
|
||||
.out_q_0__fm (q_gfpga[0]),
|
||||
.out_q_1__fm (q_gfpga[1]),
|
||||
.out_q_2__fm (q_gfpga[2]),
|
||||
.out_q_3__fm (q_gfpga[3]),
|
||||
.out_q_4__fm (q_gfpga[4]),
|
||||
.out_q_5__fm (q_gfpga[5]),
|
||||
.out_q_6__fm (q_gfpga[6]),
|
||||
.out_q_7__fm (q_gfpga[7])
|
||||
);
|
||||
|
||||
pipelined_8b_adder ref0(
|
||||
.clk (clk),
|
||||
.raddr (raddr),
|
||||
.waddr (waddr),
|
||||
.ren (ren),
|
||||
.wen (wen),
|
||||
.a (a),
|
||||
.b (b),
|
||||
.q (q_bench)
|
||||
);
|
||||
|
||||
integer nb_error = 0;
|
||||
integer count = 0;
|
||||
integer lim_max = 64 - 1;
|
||||
integer write_complete = 0;
|
||||
|
||||
//----- Initialization
|
||||
initial begin
|
||||
clk <= 1'b0;
|
||||
a <= 7'h00;
|
||||
b <= 7'h00;
|
||||
wen <= 1'b0;
|
||||
ren <= 1'b0;
|
||||
waddr <= 9'h000;
|
||||
raddr <= 9'h000;
|
||||
while(1) begin
|
||||
#2.5
|
||||
clk <= !clk;
|
||||
end
|
||||
end
|
||||
|
||||
//----- Input Stimulis
|
||||
always@(negedge clk) begin
|
||||
if(write_complete == 0) begin
|
||||
wen <= 1'b1;
|
||||
ren <= 1'b0;
|
||||
count <= count + 1;
|
||||
waddr <= waddr + 1;
|
||||
if(count == lim_max) begin
|
||||
write_complete = 1;
|
||||
end
|
||||
end else begin
|
||||
wen <= $random;
|
||||
ren <= $random;
|
||||
waddr <= $random;
|
||||
raddr <= $random;
|
||||
end
|
||||
a <= $random;
|
||||
b <= $random;
|
||||
end
|
||||
|
||||
|
||||
always@(negedge clk) begin
|
||||
if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin
|
||||
q_flag[0] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[0] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin
|
||||
q_flag[1] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[1] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin
|
||||
q_flag[2] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[2] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin
|
||||
q_flag[3] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[3] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin
|
||||
q_flag[4] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[4] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin
|
||||
q_flag[5] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[5] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin
|
||||
q_flag[6] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[6] <= 1'b0;
|
||||
end
|
||||
if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin
|
||||
q_flag[7] <= 1'b1;
|
||||
end else begin
|
||||
q_flag[7] <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always@(posedge q_flag[0]) begin
|
||||
if(q_flag[0]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[0] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[1]) begin
|
||||
if(q_flag[1]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[1] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[2]) begin
|
||||
if(q_flag[2]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[2] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[3]) begin
|
||||
if(q_flag[3]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[3] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[4]) begin
|
||||
if(q_flag[4]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[4] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[5]) begin
|
||||
if(q_flag[5]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[5] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[6]) begin
|
||||
if(q_flag[6]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[6] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
always@(posedge q_flag[7]) begin
|
||||
if(q_flag[7]) begin
|
||||
nb_error = nb_error + 1;
|
||||
$display("Mismatch on q_gfpga[7] at time = %t", $realtime);
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("pipelined_8b_adder_formal.vcd");
|
||||
$dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb);
|
||||
end
|
||||
|
||||
initial begin
|
||||
$timeformat(-9, 2, "ns", 20);
|
||||
$display("Simulation start");
|
||||
#1500 // Can be changed by the user for his need
|
||||
if(nb_error == 0) begin
|
||||
$display("Simulation Succeed");
|
||||
end else begin
|
||||
$display("Simulation Failed with %d error(s)", nb_error);
|
||||
end
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue