OpenFPGA/ERI_demo/pipelined_1b_adder.act

62 lines
1.1 KiB
Plaintext

clk 0.5 0.2
wen 0.5 0.2
wen_st0 0.5 0.2
wen_st1 0.5 0.2
ren 0.5 0.2
raddr[0] 0.5 0.2
raddr[1] 0.5 0.2
raddr[2] 0.5 0.2
raddr[3] 0.5 0.2
raddr[4] 0.5 0.2
raddr[5] 0.5 0.2
raddr[6] 0.5 0.2
raddr[7] 0.5 0.2
raddr[8] 0.5 0.2
raddr[9] 0.5 0.2
raddr[10] 0.5 0.2
waddr[0] 0.5 0.2
waddr[1] 0.5 0.2
waddr[2] 0.5 0.2
waddr[3] 0.5 0.2
waddr[4] 0.5 0.2
waddr[5] 0.5 0.2
waddr[6] 0.5 0.2
waddr[7] 0.5 0.2
waddr[8] 0.5 0.2
waddr[9] 0.5 0.2
waddr[10] 0.5 0.2
waddr_st0[0] 0.5 0.2
waddr_st0[1] 0.5 0.2
waddr_st0[2] 0.5 0.2
waddr_st0[3] 0.5 0.2
waddr_st0[4] 0.5 0.2
waddr_st0[5] 0.5 0.2
waddr_st0[6] 0.5 0.2
waddr_st0[7] 0.5 0.2
waddr_st0[8] 0.5 0.2
waddr_st0[9] 0.5 0.2
waddr_st0[10] 0.5 0.2
waddr_st1[0] 0.5 0.2
waddr_st1[1] 0.5 0.2
waddr_st1[2] 0.5 0.2
waddr_st1[3] 0.5 0.2
waddr_st1[4] 0.5 0.2
waddr_st1[5] 0.5 0.2
waddr_st1[6] 0.5 0.2
waddr_st1[7] 0.5 0.2
waddr_st1[8] 0.5 0.2
waddr_st1[9] 0.5 0.2
waddr_st1[10] 0.5 0.2
a[0] 0.5 0.2
a_st0[0] 0.5 0.2
a_st1[0] 0.5 0.2
b[0] 0.5 0.2
b_st0[0] 0.5 0.2
b_st1[0] 0.5 0.2
q[0] 0.5 0.2
q[1] 0.5 0.2
AplusB[0] 0.5 0.2
AplusB[1] 0.5 0.2
cint01 0.5 0.2
zero00 0 0