Lin
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701a7a5c52
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add test case
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2024-08-26 02:45:57 -07:00 |
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Lin
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88fa9f8d39
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add test case
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2024-08-25 23:41:19 -07:00 |
tangxifan
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05ef972911
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[test] typo
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2024-08-15 15:36:08 -07:00 |
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tangxifan
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2c35840457
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[test] add a new test to validate CHANY clock spin in DEC
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2024-08-15 14:24:31 -07:00 |
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tangxifan
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586dd1a510
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[test] add a new and strong test to validate the disable unused clock spines
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2024-08-15 10:24:58 -07:00 |
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tangxifan
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84cc7090ce
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[test] add a new test to validate that pb pin fixup impacts global net now
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2024-08-14 10:37:46 -07:00 |
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tangxifan
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542571ce89
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[test] code format
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2024-08-09 18:20:27 -07:00 |
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tangxifan
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c6246ae905
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[test] typo
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2024-08-09 17:10:51 -07:00 |
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tangxifan
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a05bfb55dd
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[test] typo
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2024-08-09 17:05:48 -07:00 |
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tangxifan
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38f1bdba4e
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[test] add a new test case
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2024-08-09 17:04:10 -07:00 |
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tangxifan
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602ab72002
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[test] add associated openfpga arch
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2024-08-09 17:01:23 -07:00 |
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tangxifan
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e6c508f081
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[test] add a new arch to validate that clock network tap supports subtiles
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2024-08-09 16:51:34 -07:00 |
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tangxifan
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1026df4890
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[test] add new tests to validate the options for undriven inputs in verilog netlists
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2024-08-06 20:58:00 -07:00 |
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tangxifan
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57adf97fd4
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[test] fixed some bugs in clock arch
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2024-08-02 18:34:59 -07:00 |
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tangxifan
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91c4336a4a
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[test] add a new testcase to validate 3-layer clock architecture
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2024-08-02 18:18:49 -07:00 |
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tangxifan
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84c2b27c7b
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[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
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2024-08-02 17:24:44 -07:00 |
chungshien
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b3c8c529d5
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Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
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2024-07-31 12:25:37 -07:00 |
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tangxifan
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3181f2d5a3
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[test] add a new test to validate multiple entry points for a clock network
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2024-07-30 14:17:14 -07:00 |
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tangxifan
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687f03fd77
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[test] add a new test to validate clock network on module named by index
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2024-07-30 14:06:53 -07:00 |
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tangxifan
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f9f9aab7d9
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[test] typo
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2024-07-30 12:50:14 -07:00 |
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tangxifan
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ad275fba44
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[test] add a new test to validate clock network entry point on a y-direction cb
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2024-07-30 12:48:35 -07:00 |
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tangxifan
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b6b038a73d
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[test] add a new arch to test y- entry point of clock network
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2024-07-30 12:40:41 -07:00 |
chungshien-chai
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ca48841ae3
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Pass in the OpenFPGA root dir
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2024-07-29 11:04:03 -07:00 |
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chungshien-chai
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3e3f089823
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Get the filepath using definition under [OpenFPGA_SHELL]
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2024-07-28 19:24:48 -07:00 |
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chungshien-chai
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0d9f1a3c6b
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Forward searching the config bit + some minor refactor
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2024-07-28 19:12:34 -07:00 |
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chungshien-chai
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933155b08f
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Update test flow
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2024-07-27 23:52:54 -07:00 |
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chungshien-chai
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fbe5ae6bd3
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Update test
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2024-07-26 02:18:08 -07:00 |
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chungshien-chai
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9641aaf6c4
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Update test
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2024-07-26 02:17:25 -07:00 |
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chungshien-chai
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2ef362d53d
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Init support overwriting bitstream
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2024-07-25 17:40:46 -07:00 |
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tangxifan
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e614ca7380
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[test] use new syntax
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2024-07-10 15:03:27 -07:00 |
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tangxifan
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977283dd34
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[core] typo
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2024-07-10 14:12:49 -07:00 |
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tangxifan
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af996e563e
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[test] add a new test to validate reset generated by internal driver through programmable clock network
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2024-07-10 14:11:06 -07:00 |
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tangxifan
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b6ff69faac
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[test] reworking the testcase to validate clock network with internal drivers
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2024-07-10 11:36:22 -07:00 |
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tangxifan
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dbe8e63f53
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[test] remove unused files
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2024-07-10 10:15:47 -07:00 |
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tangxifan
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77304164f4
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[test] rework pin loc for k4_frac_N4_tileable_fracff_40nm to save route W
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2024-07-10 10:13:41 -07:00 |
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tangxifan
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191a3d1c5e
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[test] update W
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2024-07-10 10:01:31 -07:00 |
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tangxifan
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81fe722d98
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[test] adjust W
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2024-07-09 23:49:01 -07:00 |
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tangxifan
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63f2a07c86
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[test] typo
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2024-07-09 22:54:33 -07:00 |
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tangxifan
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a16b3df063
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[test] update arch to allow clock access on CLB inputs
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2024-07-09 20:59:44 -07:00 |
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tangxifan
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43dbeafd44
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[test] typo
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2024-07-09 20:27:28 -07:00 |
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tangxifan
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9ce4b57363
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[test] typo
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2024-07-09 20:25:39 -07:00 |
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tangxifan
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e5d146a67a
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[test] add new tests to validate rst on lut and clk on lut features
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2024-07-09 20:24:23 -07:00 |
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tangxifan
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89e6a0483f
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[test] add a new benchmark to validate rst and clk on LUTs
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2024-07-09 18:45:33 -07:00 |
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tangxifan
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38bb5aa906
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[test] add a new benchmark to validate clock on LUT
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2024-07-09 18:42:39 -07:00 |
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tangxifan
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5efc9d0e00
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[test] update golden outputs
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2024-07-08 23:24:16 -07:00 |
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tangxifan
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5cb104a5f6
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[test] fixed a bug
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2024-07-08 22:04:40 -07:00 |
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tangxifan
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41839bfd7a
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[test] typo
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2024-07-08 20:21:40 -07:00 |
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tangxifan
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03c1c6f917
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[test] code format
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2024-07-08 18:35:23 -07:00 |
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tangxifan
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c7d6c3ab61
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[arch] now all the outputs of I/O can only on 1 side
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2024-07-08 18:34:13 -07:00 |
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tangxifan
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ad053cddca
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[test] code format
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2024-07-08 18:02:30 -07:00 |