tangxifan
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6dd8d347e1
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try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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42cede37fa
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add testcases on generate fabric/testbench only
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2020-06-11 19:31:01 -06:00 |
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tangxifan
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9bf91bd92a
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start testing mcnc_big20 using OpenFPGA tasks
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2020-06-11 19:30:55 -06:00 |
ganeshgore
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c31b20dc91
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Added support for simulation setting file in the task flow
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2020-06-11 19:28:13 -06:00 |
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tangxifan
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90f608baea
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changing task mcnc file for debugging (temporarily now) Will be corrected later
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2020-04-23 18:58:39 -06:00 |
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tangxifan
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f9fcc6b471
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tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
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2020-04-22 18:24:09 -06:00 |
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tangxifan
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726185cd5e
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add test cases using spypad architecture
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2020-04-22 12:56:57 -06:00 |
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tangxifan
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9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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tangxifan
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489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
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f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
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8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
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e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
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cc163081f5
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recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
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2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
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tangxifan
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2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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1e742a3676
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add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
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tangxifan
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7ba3e27371
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add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
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tangxifan
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e78643f108
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add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
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tangxifan
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59ea0a6ad5
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add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |
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tangxifan
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23aef96d3a
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add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
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tangxifan
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11e9014542
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add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
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tangxifan
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a614e5aad9
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add long adder chain to Travis CI
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2020-04-12 15:43:19 -06:00 |
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tangxifan
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f71a85a1d4
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add test cases on different routing multiplexer circuit designs to Travis CI
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2020-04-12 15:39:45 -06:00 |
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tangxifan
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214d98fbcd
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add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
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tangxifan
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148cc74d6a
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add io test cases to Travis CI
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2020-04-12 15:01:47 -06:00 |
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tangxifan
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da5af8f0e0
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try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
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28cb412359
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add test case of wide BRAM 16k to Travis CI
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2020-04-12 14:37:08 -06:00 |
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tangxifan
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5d665aa04b
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reshape bram test case
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2020-04-12 14:32:09 -06:00 |
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tangxifan
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600a48edc7
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add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
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tangxifan
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2444752de8
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add untileable test case to Travis CI
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2020-04-12 14:08:24 -06:00 |
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tangxifan
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d806ad3148
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add testcases using openfpga_shell in openfpga_flow
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2020-04-12 12:54:21 -06:00 |
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ganeshgore
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80bdb41df6
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Updated task file to run formal verification
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2020-04-11 18:30:21 -06:00 |
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tangxifan
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130b78ca74
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update arch in openfpga_flow
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2020-04-11 18:00:37 -06:00 |
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ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |
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ganeshgore
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e1db4df744
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Created task for FPGA shell run
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2020-04-06 00:35:07 -06:00 |
AurelienUoU
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c51001c853
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Add compilation verification task in openfpga_flow
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2020-01-23 13:13:23 -07:00 |
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AurelienUoU
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85c9f26a9f
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Update documentation about cmake version and graphical interface
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2020-01-22 20:46:49 -07:00 |
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tangxifan
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ef9ed2ccbc
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added duplicate_grid_pin test case
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2019-12-26 15:08:31 -07:00 |
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AurelienUoU
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32176eb352
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Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
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tangxifan
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96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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tangxifan
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a13f406918
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tweaking mcnc_big20 task run for modelsim
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2019-11-16 18:00:55 -07:00 |
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tangxifan
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4df6402241
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add python script for batch simulations
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2019-11-15 14:23:03 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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00280b835e
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reorganize regression tests
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2019-11-05 16:31:42 -07:00 |
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tangxifan
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7952d134b9
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add tree-like mux test case to regression test
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2019-11-05 16:24:39 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |