tangxifan
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59be95b227
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[core] code format
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2024-06-26 17:58:26 -07:00 |
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tangxifan
|
59404e5487
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[core] add verbose output
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2024-06-26 17:55:23 -07:00 |
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tangxifan
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576a861b8d
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[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
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2024-06-26 17:54:31 -07:00 |
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tangxifan
|
3efa97b84e
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[core] support coordinate on clock taps
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2024-06-26 17:40:11 -07:00 |
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tangxifan
|
fbece49047
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[core] fixed a bug where unexpected OPINs are added as internal drivers
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2024-06-25 12:07:19 -07:00 |
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tangxifan
|
7bcbd8a88b
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[core] code format
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2024-06-25 11:44:50 -07:00 |
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tangxifan
|
3b2c13402a
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[core] syntax
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2024-06-25 11:44:25 -07:00 |
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tangxifan
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31d4b4c402
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[core] now support add internal drivers to clock tree
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2024-06-25 11:27:22 -07:00 |
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tangxifan
|
d2053db21c
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[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
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2024-06-21 19:00:01 -07:00 |
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tangxifan
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2193f108ee
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[core] add debugging messages
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2024-06-21 18:42:35 -07:00 |
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tangxifan
|
3f08b83b3a
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[core] remove restrictions on 1 clock tree definition
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2024-06-21 17:12:10 -07:00 |
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tangxifan
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ecd31955b1
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[core] code format
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2024-06-21 17:11:32 -07:00 |
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tangxifan
|
486cd01c15
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[core] now clock graph builder supports two types of switches
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2024-06-21 16:54:22 -07:00 |
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tangxifan
|
ad8ad25250
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[core] format
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2024-05-31 19:44:40 -07:00 |
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tangxifan
|
93ebbef851
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[core] fixed a bug
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2024-05-31 19:42:50 -07:00 |
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tangxifan
|
514ec2f02e
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[core] code format
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2024-05-31 18:02:46 -07:00 |
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tangxifan
|
2d10be9edb
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[core] code comments
|
2024-05-31 18:00:24 -07:00 |
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tangxifan
|
f9cd01636d
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[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
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2024-05-31 17:57:36 -07:00 |
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tangxifan
|
212abecc27
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[core] syntax
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2024-05-31 17:41:49 -07:00 |
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tangxifan
|
348d474bfd
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[core] more debuggin messages
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2024-05-31 17:40:19 -07:00 |
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tangxifan
|
c565264e7d
|
[core] more debuggin messages
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2024-05-31 17:14:42 -07:00 |
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tangxifan
|
6dc31bf892
|
[core] fixed a bug on missing net sync up during repack
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2024-05-31 16:53:59 -07:00 |
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tangxifan
|
5b35f567d2
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[core] detailed messages to trace why some nets are no sync
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2024-05-31 16:00:10 -07:00 |
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tangxifan
|
5adc1be204
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[core] syntax
|
2024-05-31 15:50:27 -07:00 |
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tangxifan
|
a9ccc277bd
|
[core] more debugging message
|
2024-05-31 15:49:34 -07:00 |
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tangxifan
|
937e279c59
|
[core] adding more debugging messages
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2024-05-31 15:43:51 -07:00 |
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tangxifan
|
7a7fc679a8
|
[core] enable more debugging message in repacker
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2024-05-31 14:52:59 -07:00 |
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tangxifan
|
edb50f1b4d
|
[core] update debug messages
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2024-05-31 14:37:46 -07:00 |
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tangxifan
|
48c0b4b219
|
[core] fixed a bug where net name is not shown correctly on wire LUTs
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2024-05-31 12:45:12 -07:00 |
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tangxifan
|
74e94b855e
|
[core] fixed a bug where gsb OPIN name does not match the switch block module
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2024-05-29 10:27:10 -07:00 |
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tangxifan
|
52ae484a7c
|
[core] fixed a bug on messed up wire connections for OPINs
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2024-05-20 13:50:31 -07:00 |
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tangxifan
|
ca6e2f9831
|
[core] code format
|
2024-05-20 13:41:35 -07:00 |
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tangxifan
|
4a791249bf
|
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
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2024-05-20 12:52:07 -07:00 |
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tangxifan
|
b554a3d855
|
[core] code format
|
2024-05-19 17:24:38 -07:00 |
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tangxifan
|
56aaa6a1f4
|
[core] sytax
|
2024-05-19 17:23:48 -07:00 |
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tangxifan
|
065d77c679
|
[core] supporting opin connection to cb in tiles
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2024-05-19 17:04:24 -07:00 |
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tangxifan
|
9079056871
|
[core] now connect OPIN to CB in top-level module
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2024-05-19 14:27:36 -07:00 |
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tangxifan
|
918bf79ca3
|
[core] update vtr and developing caches for OPIN lists just for connection blocks
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2024-05-19 14:10:00 -07:00 |
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tangxifan
|
772da3006b
|
[core] code format
|
2024-05-18 22:19:17 -07:00 |
|
tangxifan
|
304f34525e
|
[core] syntax
|
2024-05-18 22:17:52 -07:00 |
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tangxifan
|
b533ea4060
|
[core] now cb module include OPIN nodes
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2024-05-18 22:00:02 -07:00 |
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tangxifan
|
926b9e9739
|
[core] code format
|
2024-05-18 12:33:19 -07:00 |
|
tangxifan
|
3b93bea3d1
|
[core] syntax
|
2024-05-18 12:29:38 -07:00 |
|
tangxifan
|
0d8c21ca84
|
[core] add new type 'part_of_cb' for tile direct connections
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2024-05-17 18:59:53 -07:00 |
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tangxifan
|
7848bdaeac
|
[core] code format
|
2024-05-09 22:50:49 -07:00 |
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tangxifan
|
5f37d63061
|
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
|
2024-05-09 19:38:26 -07:00 |
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tangxifan
|
7dc2c4951c
|
[core] add missing header required by clang-11+
|
2024-05-05 21:56:56 -07:00 |
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tangxifan
|
3d8107487c
|
[core] code format
|
2024-05-03 10:21:39 -07:00 |
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tangxifan
|
c7501cb9b7
|
[core] fixed the bugs when there are module renaming
|
2024-05-03 10:20:19 -07:00 |
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tangxifan
|
f41a5e8b89
|
[core] fixed some bugs
|
2024-05-02 22:49:06 -07:00 |